公开(公告)号：US20220374150A1

公开(公告)日：2022-11-24

申请号：US17748644

申请日：2022-05-19

Applicant: Micron Technology, Inc.

Inventor： Antonino Caprì ,  Emanuele Confalonieri ,  Simone Corbetta ,  Michela Spagnolo

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods related to an adjustable timer component are described. A memory device includes, a memory controller coupled to the memory device comprising an adjustable timer component. The adjustable timer component is configured to receive a timer generation request and, responsive to receiving the request, store in a cache an active timer entry corresponding to a particular first address, generate a timer corresponding to an active timer entry and the particular first address, and monitor the timer to determine when the timer expires. Responsive to the expiration of the timer, dequeue the timer entry and invalidate the timer entry stored in the cache. The memory device can also include command logic configured to, prior to issuing a second command, query the cache of the adjustable timer component to determine if the cache includes an active timer entry corresponding to the particular second address.

公开(公告)号：US20220350533A1

公开(公告)日：2022-11-03

申请号：US17244734

申请日：2021-04-29

Applicant: Micron Technology, Inc.

Inventor： Federica Cresci ,  Nicola Del Gatto ,  Massimiliano Patriarca ,  Maddalena Calzolari ,  Michela Spagnolo ,  Massimiliano Turconi

IPC: G06F3/06

Abstract: Methods, systems, and devices for low latency storage based on data size are described. A memory system may include logic, a processor, a first memory, and a second memory. The logic may be configured to receive commands, or data, or both, from a host system. The first memory and the second memory may be coupled with the processor. The processor may be configured to store, or to cause the storage of, data for commands associated with data that are smaller than a threshold in the first memory and to store data for commands associated with data that are larger than the threshold in the second memory. A first communication path between the logic and the first memory may be associated with a faster transfer speed than a second communication path between the logic and the second memory.

公开(公告)号：US11720284B2

公开(公告)日：2023-08-08

申请号：US17244734

申请日：2021-04-29

Applicant: Micron Technology, Inc.

Inventor： Federica Cresci ,  Nicola Del Gatto ,  Massimiliano Patriarca ,  Maddalena Calzolari ,  Michela Spagnolo ,  Massimiliano Turconi

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0679

Abstract: Methods, systems, and devices for low latency storage based on data size are described. A memory system may include logic, a processor, a first memory, and a second memory. The logic may be configured to receive commands, or data, or both, from a host system. The first memory and the second memory may be coupled with the processor. The processor may be configured to store, or to cause the storage of, data for commands associated with data that are smaller than a threshold in the first memory and to store data for commands associated with data that are larger than the threshold in the second memory. A first communication path between the logic and the first memory may be associated with a faster transfer speed than a second communication path between the logic and the second memory.