公开(公告)号：US08767457B2

公开(公告)日：2014-07-01

申请号：US14043476

申请日：2013-10-01

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Mike N. Nguyen

IPC: G11C11/34 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L27/10802 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/7841

Abstract: An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.

Abstract translation: 公开了一种具有浮体的存储单元的装置。 存储单元可以包括绝缘层上的晶体管，晶体管包括源极和漏极。 存储单元还可以包括浮动体，其包括位于源极和漏极之间的第一区域，远离源极和漏极中的每一个定位的第二区域，以及延伸穿过绝缘层并且将第一区域耦合到第二区域的第二区域 地区。 另外，存储单元可以包括至少部分地围绕第二区域并被配置为可操作地耦合到偏置电压的偏置栅极。 此外，存储单元可以包括多个电介质层，其中第二区域的每个外部垂直表面具有与其相邻的多个电介质层。

公开(公告)号：US09048131B2

公开(公告)日：2015-06-02

申请号：US14289162

申请日：2014-05-28

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Mike N. Nguyen

IPC: G11C11/34 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/10802 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/7841

Abstract: An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.

Abstract translation: 公开了一种具有浮体的存储单元的装置。 存储单元可以包括绝缘层上的晶体管，晶体管包括源极和漏极。 存储单元还可以包括浮动体，其包括位于源极和漏极之间的第一区域，远离源极和漏极中的每一个定位的第二区域，以及延伸穿过绝缘层并且将第一区域耦合到第二区域的第二区域 地区。 另外，存储单元可以包括至少部分地围绕第二区域并被配置为可操作地耦合到偏置电压的偏置栅极。 此外，存储单元可以包括多个电介质层，其中第二区域的每个外部垂直表面具有与其相邻的多个电介质层。

公开(公告)号：US20140269047A1

公开(公告)日：2014-09-18

申请号：US14289162

申请日：2014-05-28

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Mike N. Nguyen

IPC: H01L27/108 ,  H01L29/66

CPC classification number: H01L27/10802 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/7841

Abstract: An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.

Abstract translation: 公开了一种具有浮体的存储单元的装置。 存储单元可以包括绝缘层上的晶体管，晶体管包括源极和漏极。 存储单元还可以包括浮动体，其包括位于源极和漏极之间的第一区域，远离源极和漏极中的每一个定位的第二区域，以及延伸穿过绝缘层并且将第一区域耦合到第二区域的第二区域 地区。 另外，存储单元可以包括至少部分地围绕第二区域并被配置为可操作地耦合到偏置电压的偏置栅极。 此外，存储单元可以包括多个电介质层，其中第二区域的每个外部垂直表面具有与其相邻的多个电介质层。

公开(公告)号：US20140035015A1

公开(公告)日：2014-02-06

申请号：US14043476

申请日：2013-10-01

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Mike N. Nguyen

IPC: H01L27/108

CPC classification number: H01L27/10802 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/7841

Abstract: An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.

Abstract translation: 公开了一种具有浮体的存储单元的装置。 存储单元可以包括绝缘层上的晶体管，晶体管包括源极和漏极。 存储单元还可以包括浮动体，其包括位于源极和漏极之间的第一区域，远离源极和漏极中的每一个定位的第二区域，以及延伸穿过绝缘层并且将第一区域耦合到第二区域的第二区域 地区。 另外，存储单元可以包括至少部分地围绕第二区域并被配置为可操作地耦合到偏置电压的偏置栅极。 此外，存储单元可以包括多个电介质层，其中第二区域的每个外部垂直表面具有与其相邻的多个电介质层。