公开(公告)号：US20240071819A1

公开(公告)日：2024-02-29

申请号：US18234111

申请日：2023-08-15

Applicant: Micron Technology, Inc.

Inventor： Chandra S. Tiwari ,  Jivaan Kishore Jhothiraman ,  Rutuparna Narulkar ,  Nayan Chakravarty ,  Pengyuan Zheng ,  Hiroaki Iuchi

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76831 ,  H01L23/5226 ,  H10B43/27

Abstract: A variety of applications can include apparatus having a memory device structured with a three-dimensional array of memory cells and one or more vertical metal contacts extending through levels of the memory device, where the one or more vertical metal contacts are formed with reduced stress. Each of the one or more vertical metal contacts can be constructed by forming a liner on walls of an opening in a dielectric, where the opening extends through the levels for the memory device, and forming a metal composition adjacent the liner and filling the opening with the metal composition. The liner can be removed from at least a portion of the walls of the dielectric, where the liner has a composition correlated to the metal composition such that removal of the liner reduces stress on the metal composition.