MEMORY SUB-SYSTEM SLOW PROGRAM DETECTION

    公开(公告)号:US20240427518A1

    公开(公告)日:2024-12-26

    申请号:US18680736

    申请日:2024-05-31

    Abstract: An example apparatus can include a program component. The program component can program each of a plurality of planes during different time periods subsequent to performing a multi-plane programming on a non-volatile memory array. The program component can monitor a program pulse count for each of the respective plurality of planes per super block. The program component can, in response to the program pulse count for a respective block within one of the plurality of planes being above a threshold pulse count, determine that the respective block is a bad block.

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