公开(公告)号：US20230325323A1

公开(公告)日：2023-10-12

申请号：US18178105

申请日：2023-03-03

Applicant: Micron Technology, Inc.

Inventor： Sushanth Bhushan ,  Dheeraj Srinivasan

IPC: G06F12/0891

CPC classification number: G06F12/0891

Abstract: Control logic in a memory device executes a first programming operation to program the set of memory cells to a set of programming levels. A first cache ready signal is generated, the first cache ready signal indicating to a host system to send first data associated with a second programming operation to an input/output (I/O) data cache of the memory device. A first encoded data value and a second encoded data value associated with each memory cell of the set of memory cells are generated. A second cache ready signal is generated, the second cache ready signal indicating to the host system to send second data associated with the next programming operation to the I/O data cache. The first data associated with the second programming operation is caused to be stored in a third data cache of the cache storage. A third cache ready signal is generated, the third cache ready signal indicating to the host system to send third data associated with the second programming operation to the I/O data cache.

公开(公告)号：US20240378156A1

公开(公告)日：2024-11-14

申请号：US18779666

申请日：2024-07-22

Applicant: Micron Technology, Inc.

Inventor： Sushanth Bhushan ,  Dheeraj Srinivasan

IPC: G06F12/0891

Abstract: Control logic in a memory device executes a first programming operation to program the set of memory cells to a set of programming levels. A first cache ready signal is generated, the first cache ready signal indicating to a host system to send first data associated with a second programming operation to an input/output (I/O) data cache of the memory device. A second cache ready signal is generated, the second cache ready signal indicating to the host system to send second data associated with the next programming operation to the I/O data cache. The first data associated with the second programming operation is caused to be stored in a cache storage of the memory device.

公开(公告)号：US12079134B2

公开(公告)日：2024-09-03

申请号：US18178105

申请日：2023-03-03

Applicant: Micron Technology, Inc.

Inventor： Sushanth Bhushan ,  Dheeraj Srinivasan

IPC: G06F12/08 ,  G06F12/0891

CPC classification number: G06F12/0891

Abstract: Control logic in a memory device executes a first programming operation to program the set of memory cells to a set of programming levels. A first cache ready signal is generated, the first cache ready signal indicating to a host system to send first data associated with a second programming operation to an input/output (I/O) data cache of the memory device. A first encoded data value and a second encoded data value associated with each memory cell of the set of memory cells are generated. A second cache ready signal is generated, the second cache ready signal indicating to the host system to send second data associated with the next programming operation to the I/O data cache. The first data associated with the second programming operation is caused to be stored in a third data cache of the cache storage. A third cache ready signal is generated, the third cache ready signal indicating to the host system to send third data associated with the second programming operation to the I/O data cache.