公开(公告)号：US20210096756A1

公开(公告)日：2021-04-01

申请号：US16662943

申请日：2019-10-24

Applicant: Micron Technology, Inc.

Inventor： Suresh RAJGOPAL ,  Zhi Kai FENG ,  Yue WEI

IPC: G06F3/06

Abstract: A memory device protection manager determines an estimated remaining life of a physical memory device. By comparing the estimated remaining life of the physical memory device to a threshold value, the memory device protection manager determines whether a drive protection condition has been triggered. When the drive protection condition is triggered, the memory device protection manager modifies a write performance for subsequent data units to a modified write performance rate. The modified write performance rate is an upper limit on the write performance for the subsequent data units.

公开(公告)号：US20210096755A1

公开(公告)日：2021-04-01

申请号：US16666351

申请日：2019-10-28

Applicant: Micron Technology, Inc.

Inventor： Suresh RAJGOPAL ,  Ling WANG ,  Yue WEI ,  Vamsi Pavan RAYAPROLU

IPC: G06F3/06

Abstract: A method is implemented for a memory sub-system that detects a sequential write pattern in a write sequence for a memory device in a set of commands received from a host, detects current bandwidth utilization deviating from a write bandwidth utilization performance target, in response to detecting the sequential write pattern, and adjusts write bandwidth utilization to conform to the write bandwidth utilization target, in response to detecting the current bandwidth utilization deviating from the write bandwidth utilization performance target.

公开(公告)号：US20250044947A1

公开(公告)日：2025-02-06

申请号：US18925770

申请日：2024-10-24

Applicant: Micron Technology, Inc.

Inventor： Guang SHEN ,  Yue WEI

IPC: G06F3/06

Abstract: Implementations described herein relate to memory command assignment based on command processor workload. In some implementations, a memory device may determine a first command type of a first memory command. The memory device may identify a first command processor, associated with the first command type, that is one of multiple command processors configured to execute memory commands. The first command processor may be configured to execute only commands having the first command type unless a computational credit condition, associated with another command processor, is satisfied. The memory device may determine that a cumulative computational credit value associated with the first command processor does not satisfy a condition. The memory device may assign the first memory command to the first command processor for execution based on determining that the cumulative computational credit value associated with the first command processor does not satisfy the condition.

公开(公告)号：US20240061585A1

公开(公告)日：2024-02-22

申请号：US17821894

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Guang SHEN ,  Yue WEI

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0635 ,  G06F3/0679

Abstract: Implementations described herein relate to memory command assignment based on command processor workload. In some implementations, a memory device may determine a first command type of a first memory command. The memory device may identify a first command processor, associated with the first command type, that is one of multiple command processors configured to execute memory commands. The first command processor may be configured to execute only commands having the first command type unless a computational credit condition, associated with another command processor, is satisfied. The memory device may determine that a cumulative computational credit value associated with the first command processor does not satisfy a condition. The memory device may assign the first memory command to the first command processor for execution based on determining that the cumulative computational credit value associated with the first command processor does not satisfy the condition.