公开(公告)号：US20230068011A1

公开(公告)日：2023-03-02

申请号：US17895565

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Yasushi Matsubara ,  Yusuke Yono ,  Donald Martin Morgan ,  Nobuo Yamamoto

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/20 ,  G11C7/18

Abstract: Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.