Interactive CAD apparatus for designing packaging of logic circuit design
    1.
    发明授权
    Interactive CAD apparatus for designing packaging of logic circuit design 失效
    用于设计逻辑电路设计封装的交互式CAD设备

    公开(公告)号:US6117183A

    公开(公告)日:2000-09-12

    申请号:US894695

    申请日:1997-08-26

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5031 G06F17/5068

    摘要: Disclosed is an interactive CAD apparatus for logic circuit packaging design, wherein provisions are made to display delay times in real time when a component is being moved, so that error-contributing components and interconnections can be easily identified and the optimum position can be easily determined. The apparatus includes: a component moving unit, responsive to an operator's instruction, for moving a component on a display screen where a component placement diagram is displayed; an associated path extraction unit for extracting a signal path associated with the component being moved by the component moving unit; a temporary position calculation unit for calculating temporary position data representing a placement position corresponding to the position of the component on the display screen at prescribed intervals of time when the component is being moved by the component moving unit; an associated path delay calculation unit for successively calculating delay values for the signal path extracted by the associated path extraction unit, based on the temporary position data calculated by the temporary position calculation unit; and an associated path delay display unit for successively displaying the delay values calculated by the associated path delay calculation unit.

    摘要翻译: PCT No.PCT / JP97 / 00015 Sec。 371日期:1997年8月26日 102(e)日期1997年8月26日PCT 1997年1月8日PCT公布。 公开号WO97 / 25681 日期1997年7月17日公开是一种用于逻辑电路封装设计的交互式CAD设备,其中规定了在组件移动时实时显示延迟时间,从而可以容易地识别出错误的组件和互连,并且最优 位置可以很容易地确定。 该装置包括:组件移动单元,响应于操作者的指示,用于移动显示屏幕上的组件,其中显示组件放置图; 相关联的路径提取单元,用于提取与由所述分量移动单元移动的分量相关联的信号路径; 临时位置计算单元,用于当由所述分量移动单元移动所述分量时,以规定的时间间隔计算表示与所述分量在所述显示屏幕上的位置相对应的放置位置的临时位置数据; 相关联的路径延迟计算单元,用于基于由临时位置计算单元计算的临时位置数据连续地计算由相关联的路径提取单元提取的信号路径的延迟值; 以及相关联的路径延迟显示单元,用于连续显示由相关联的路径延迟计算单元计算的延迟值。