摘要:
Disclosed is an interactive CAD apparatus for logic circuit packaging design, wherein provisions are made to display delay times in real time when a component is being moved, so that error-contributing components and interconnections can be easily identified and the optimum position can be easily determined. The apparatus includes: a component moving unit, responsive to an operator's instruction, for moving a component on a display screen where a component placement diagram is displayed; an associated path extraction unit for extracting a signal path associated with the component being moved by the component moving unit; a temporary position calculation unit for calculating temporary position data representing a placement position corresponding to the position of the component on the display screen at prescribed intervals of time when the component is being moved by the component moving unit; an associated path delay calculation unit for successively calculating delay values for the signal path extracted by the associated path extraction unit, based on the temporary position data calculated by the temporary position calculation unit; and an associated path delay display unit for successively displaying the delay values calculated by the associated path delay calculation unit.