公开(公告)号：US20060212285A1

公开(公告)日：2006-09-21

申请号：US11153419

申请日：2005-06-16

申请人： Minoru Kawarabayashi ,  Takayuki Shimamura ,  Tatekuni Onoue ,  Yasuyuki Umezaki

发明人： Minoru Kawarabayashi ,  Takayuki Shimamura ,  Tatekuni Onoue ,  Yasuyuki Umezaki

IPC分类号： G06F9/455

CPC分类号： G06F11/261

摘要： A speed converting apparatus with a load controlling function comprises a first interface unit operating for an emulation device according to a system clock of the emulation device, a second interface unit operating for an arithmetic unit according to a system clock of the arithmetic unit, and a load controlling unit controlling at least either a load of a request outputted to the emulation device on the emulation device or a load of a request outputted to the arithmetic unit on the arithmetic unit. In performance verification or connection verification of a target to be verified, the speed converting apparatus can vary a load of a request issued to the target to be verified on the target or a load issued to a verification device on the verification device, while absorbing a difference in operation speed between the target to be verified and the verification device.

摘要翻译： 具有负载控制功能的速度转换装置包括根据仿真装置的系统时钟为仿真装置操作的第一接口单元，根据运算单元的系统时钟对运算单元运行的第二接口单元，以及 负载控制单元至少控制在仿真装置上输出到仿真装置的请求的负载或者在运算单元上输出到运算单元的请求的负载。 在要验证的目标的性能验证或连接验证中，速度转换装置可以在发送给目标上的目标的请求的负载或发送给验证装置上的验证装置的负载上，同时吸收 待验证目标与验证装置之间的运行速度差。

公开(公告)号：US08812288B2

公开(公告)日：2014-08-19

申请号：US11153419

申请日：2005-06-16

申请人： Minoru Kawarabayashi ,  Takayuki Shimamura ,  Tatekuni Onoue ,  Yasuyuki Umezaki

发明人： Minoru Kawarabayashi ,  Takayuki Shimamura ,  Tatekuni Onoue ,  Yasuyuki Umezaki

IPC分类号： G06F9/455

CPC分类号： G06F11/261

摘要： A speed converting apparatus with a load controlling function comprises a first interface unit operating for an emulation device according to a system clock of the emulation device, a second interface unit operating for an arithmetic unit according to a system clock of the arithmetic unit, and a load controlling unit controlling at least either a load of a request outputted to the emulation device on the emulation device or a load of a request outputted to the arithmetic unit on the arithmetic unit. In performance verification or connection verification of a target to be verified, the speed converting apparatus can vary a load of a request issued to the target to be verified on the target or a load issued to a verification device on the verification device, while absorbing a difference in operation speed between the target to be verified and the verification device.

摘要翻译： 具有负载控制功能的速度转换装置包括根据仿真装置的系统时钟为仿真装置操作的第一接口单元，根据运算单元的系统时钟对运算单元运行的第二接口单元，以及 负载控制单元至少控制在仿真装置上输出到仿真装置的请求的负载或者在运算单元上输出到运算单元的请求的负载。 在要验证的目标的性能验证或连接验证中，速度转换装置可以在发送给目标上的目标的请求的负载或发送给验证装置上的验证装置的负载上，同时吸收 待验证目标与验证装置之间的运行速度差。

公开(公告)号：US20080082760A1

公开(公告)日：2008-04-03

申请号：US11829365

申请日：2007-07-27

申请人： Tatekuni Onoue

发明人： Tatekuni Onoue

IPC分类号： G06F12/00

CPC分类号： G06F11/30 ,  G06F11/0766

摘要： An event holding circuit configured to monitor plural monitored boards, write collected event information, and hold the event information until a processor reads the event information, the event holding circuit includes a holding circuit including an OR gate, so that a logical sum output of the collected event information and holding event information is written in a memory where written contents until the last time have been read from an address area of the memory where the event information is to be written.

摘要翻译： 一种事件保持电路，被配置为监视多个被监视的电路板，写入所收集的事件信息，并保持事件信息，直到处理器读取事件信息为止，事件保持电路包括一个包括或门的保持电路，使得逻辑和输出 收集的事件信息和保持事件信息被写入存储器，其中写入的内容直到从写入事件信息的存储器的地址区域中读取最后一次。