公开(公告)号：US20240291647A1

公开(公告)日：2024-08-29

申请号：US18652844

申请日：2024-05-02

Applicant: Mohan Kumar JINDAL ,  Shailja JINDAL

Inventor： Mohan Kumar JINDAL ,  Srirama Chandra Murthy PRATAPA ,  Sumit Manoj KAVATHEKAR ,  Ashish Shridhar JADHAO ,  Jaspritam SINGH ,  Sanchith Vakkalaganti MAHESH ,  Mayuri Uday DAWANDE ,  Pratiksha Ishwar JONDHALE ,  Shon Pravin TAWARE ,  Adithi L ,  Ravindra Madan LANDE ,  Sesha Sowjanya BATTULA ,  Akanksha Kishor BEDEKAR ,  Rakshanda Baban TIDKE ,  SaiRangesh THIRUNAGARAM ,  Kanan Subramanium NADAR ,  Swapnil Sopanrao MORE ,  Nikunj Mukeshbhai VAGHANI ,  Sahana NAZAR ,  Sravani RANAM ,  Jeevan Kumar Reddy PALAGANI ,  Hari Prasad BADHAM ,  Dinesha SHIVANGOUDRA ,  Achyuth Goud YESU ,  Sai Charan PERUMALLA ,  Vamsi Krishna KANUMURI

IPC: H04L9/08 ,  G06F21/31

CPC classification number: H04L9/0877 ,  G06F21/31

Abstract: Disclosed is a data processing apparatus (104) including a key memory (123) to store a list of cryptography keys, a key USB subunit (132) to enable receiving one or more cryptography keys from a user to generate an updated list of cryptography keys, a cryptography unit (122) to encrypt first data to generate second data based on a cryptography key randomly selected from the updated list of cryptography keys, and decrypt the second data to generate the first data, based on the key, and a USB subunit (130) to enable exchange of the first data between a first external device (104) and the cryptography unit (122), and the second data between a second external device (106) and the cryptography unit (122). The data processing apparatus (102) is implemented on at least one of, a Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuits (ASICs).