公开(公告)号：US07032192B2

公开(公告)日：2006-04-18

申请号：US10444232

申请日：2003-05-22

申请人： Mukul R. Prasad ,  Rajarshi Mukherjee ,  Jawahar Jain ,  Kelvin K. C. Ng

发明人： Mukul R. Prasad ,  Rajarshi Mukherjee ,  Jawahar Jain ,  Kelvin K. C. Ng

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： Performing latch mapping includes receiving an initial circuit model representing a first circuit and a second circuit and generating an initial latch mapping for the initial circuit model. The following is repeated until a next latch mapping is at least similar to a current latch mapping to yield a final latch mapping. A current circuit model is constructed according to a previous circuit model. Current potentially equivalent node sets associated with the current circuit model are established in accordance with previous potentially equivalent node sets, where each potentially equivalent node set includes potentially equivalent nodes. Equivalence of the current potentially equivalent node sets is validated, and a current latch mapping is verified in accordance with the validated current potentially equivalent node sets to generate a next latch mapping. The final latch mapping is reported.

摘要翻译： 执行锁存映射包括接收表示第一电路和第二电路的初始电路模型，并为初始电路模型生成初始锁存器映射。 重复以下操作，直到下一个锁存器映射至少类似于当前锁存器映射以产生最终的锁存器映射。 根据先前的电路模型构建电流电路模型。 根据先前的潜在等效的节点集建立与当前电路模型相关联的当前潜在等价的节点集，其中每个潜在的等效节点集包括潜在的等效节点。 验证当前潜在等效的节点集的等效性，并且根据经验证的当前潜在的等效节点集来验证当前的锁存映射以生成下一个锁存映射。 报告最后的锁存映射。