公开(公告)号：US20240203655A1

公开(公告)日：2024-06-20

申请号：US18586825

申请日：2024-02-26

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Seiji HIDAKA ,  Atsutaka MORI ,  Yukihiro FUJITA

IPC: H01G4/232 ,  G06F30/3323 ,  H01G4/30

CPC classification number: H01G4/232 ,  G06F30/3323 ,  H01G4/30

Abstract: A method for creating an equivalent circuit model of a multi-terminal capacitor including staggered positive and negative outer electrode terminals includes measuring S parameters of the multi-terminal capacitor, deriving a total impedance of the multi-terminal capacitor based on measured S parameter measurement values, creating a two-terminal equivalent circuit model from the derived total impedance of the multi-terminal capacitor, deriving a unit-cell equivalent circuit model from the created two-terminal equivalent circuit model, creating a three-dimensional grid topology by combining the derived unit-cell equivalent circuit model and an equivalent circuit model of a parasitic component including capacitive and inductive circuit elements, and setting terminals of the multi-terminal capacitor at nodes in the created three-dimensional grid topology.

公开(公告)号：US20240202414A1

公开(公告)日：2024-06-20

申请号：US18586780

申请日：2024-02-26

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Seiji HIDAKA ,  Atsutaka MORI ,  Yukihiro FUJITA

IPC: G06F30/367 ,  G06F119/06

CPC classification number: G06F30/367 ,  G06F2119/06

Abstract: A method for creating an equivalent circuit model of a multi-terminal capacitor including staggered positive and negative outer electrode terminals includes measuring S parameters of the multi-terminal capacitor, deriving a total impedance of the multi-terminal capacitor based on S-parameter measurement values, creating a two-terminal equivalent circuit model from the derived total impedance of the multi-terminal capacitor, deriving a unit-cell equivalent circuit model from the created two-terminal equivalent circuit model, creating a two-dimensional grid topology by combining the derived unit-cell equivalent circuit model and a parasitic-component equivalent circuit model, and setting terminals of the multi-terminal capacitor at nodes in the created two-dimensional grid topology.