公开(公告)号：US20240387113A1

公开(公告)日：2024-11-21

申请号：US18786661

申请日：2024-07-29

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kengo KAKOMURA ,  Yukihiro FUJITA ,  Seiji HIDAKA

IPC: H01G4/236 ,  H01G4/008 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30

Abstract: A multilayer ceramic capacitor includes a capacitor body including dielectric layers, first and second inner electrodes, first and second via conductors, and first and second outer electrodes. In a reference layout in which m×n (m and n are each a natural number of 4 or more) virtual lattice points are set in a view of the capacitor body seen in a lamination direction, and in which the first and second via conductors are arranged at all the virtual lattice points, the first and second via conductors are not arranged at least in a portion of (m-2)×(n-2) of the virtual lattice points located inside outermost peripheral virtual lattice points.