公开(公告)号：US3810113A

公开(公告)日：1974-05-07

申请号：US28127372

申请日：1972-08-17

Applicant: NAT RES DEV

Inventor： JORDAN J

IPC: G06F17/18 ,  G06F17/15 ,  G06F7/02

CPC classification number: G06F17/15

Abstract: A computing apparatus comprises a set of counters corresponding to different stages of a shift register having a serial input. A binary signal is applied to this input, and the inputs of the counters are gated so that each counts only when the state of the corresponding stage satisfies a particular condition, for example coincidence with the current state of another binary signal. Once the count for any counter has reached a given value a signal is generated indicating for which of the counters this has occurred. A principal use is for identifying the time delay between two related noise signals.

Abstract translation: 计算装置包括与具有串行输入的移位寄存器的不同级相对应的一组计数器。 二进制信号被施加到该输入，并且计数器的输入被选通，使得每个计数器只有当相应级的状态满足特定条件时才计数，例如与另一个二进制信号的当前状态一致。 一旦任何计数器的计数达到给定值，就产生一个信号，指示哪个计数器已经发生。 主要用途是识别两个相关噪声信号之间的时间延迟。