公开(公告)号：US20140131716A1

公开(公告)日：2014-05-15

申请号：US13744594

申请日：2013-01-18

Applicant: NATIONAL APPLIED RESEARCH LABORATORIES

Inventor： Jia-Min Shieh ,  Yu-Chung Lien ,  Wen-Hsien Huang ,  Chang-Hong Shen ,  Min-Cheng Chen ,  Ci-Ling Pan

IPC: H01L29/792

CPC classification number: H01L29/66825 ,  B82Y40/00 ,  H01L29/40114 ,  H01L29/42332 ,  H01L29/7881 ,  Y10S977/774

Abstract: A memory device comprises a substrate, a tunnel oxide layer, a charge trapping layer, a block oxide layer, a plurality of conductive quantum dots, a metal gate and a source/drain structure. The tunnel oxide layer is disposed on the substrate and has a thickness substantially less than or equal to 2 nm. The charge trapping layer is disposed on the tunnel oxide layer. The quantum dots are embedded in the charge trapping layer. The block oxide layer is disposed on the charge trapping layer. The metal gate essentially consisting of aluminum (Al), copper (Cu), tantalum nitride (TiN), titanium nitride (TaN), aluminum-silicon-copper (Al—Si—Cu) alloys or the arbitrary combinations thereof is disposed on the block oxide layer. The source/drain structure is disposed in the substrate.

Abstract translation: 存储器件包括衬底，隧道氧化物层，电荷俘获层，块状氧化物层，多个导电量子点，金属栅极和源极/漏极结构。 隧道氧化物层设置在基板上，其厚度基本上小于或等于2nm。 电荷捕获层设置在隧道氧化物层上。 量子点嵌入电荷俘获层中。 块状氧化物层设置在电荷俘获层上。 基本上由铝（Al），铜（Cu），氮化钽（TiN），氮化钛（TaN），铝 - 硅 - 铜（Al-Si-Cu）合金或其任意组合组成的金属栅极设置在 块状氧化物层。 源极/漏极结构设置在衬底中。