公开(公告)号：US20140077844A1

公开(公告)日：2014-03-20

申请号：US14082700

申请日：2013-11-18

Applicant: Nihon Dempa Kogyo Co., Ltd.

Inventor： Yasuo Kitayama ,  Hiroyuki Demura ,  Naoki Onishi

IPC: H03B21/00

CPC classification number: H03B21/00 ,  H03G1/0058 ,  H03G3/30 ,  H03L5/00

Abstract: To provide, in a frequency synthesizer including: a variable attenuator provided at a subsequent stage of a voltage controlled oscillator; a detector; and a control unit outputting a control voltage for adjusting an attenuation amount of the variable attenuator via a digital/analog converter in accordance with a detection voltage, a technology with which a spurious due to a change in an output of the digital/analog converter can be suppressed. A low-pass filter is provided between an output side of a digital/analog converter and a variable attenuator to cut a frequency component corresponding to an overshoot generated when an output of the digital/analog converter is changed. Further, a period of time from when a control unit outputs a control voltage to when it reads a signal level detected by a detector is set to a period of time longer than a time constant of the low-pass filter determined by a cut-off frequency of the low-pass filter so that no influence is exerted on an operation of automatically controlling the signal level.

Abstract translation: 提供一种频率合成器，包括：设置在压控振荡器的后续级的可变衰减器; 检测器 以及控制单元，其根据检测电压输出用于经由数字/模拟转换器调整可变衰减器的衰减量的控制电压，由于数字/模拟转换器的输出的变化引起的寄生的杂散技术 被压制 在数字/模拟转换器的输出侧和可变衰减器之间提供低通滤波器，以便在数字/模拟转换器的输出改变时产生的过冲相应的剪切频率分量。 此外，从控制单元输出控制电压到读取检测器检测到的信号电平的时间段被设置为比由截止器确定的低通滤波器的时间常数更长的时间段 低通滤波器的频率，从而不会对自动控制信号电平的操作产生影响。

公开(公告)号：US09300250B2

公开(公告)日：2016-03-29

申请号：US14082700

申请日：2013-11-18

Applicant: NIHON DEMPA KOGYO CO., LTD.

Inventor： Yasuo Kitayama ,  Hiroyuki Demura ,  Naoki Onishi

IPC: H03B21/00 ,  H03G1/00 ,  H03G3/30 ,  H03L5/00

CPC classification number: H03B21/00 ,  H03G1/0058 ,  H03G3/30 ,  H03L5/00

Abstract: To provide, in a frequency synthesizer including: a variable attenuator provided at a subsequent stage of a voltage controlled oscillator; a detector; and a control unit outputting a control voltage for adjusting an attenuation amount of the variable attenuator via a digital/analog converter in accordance with a detection voltage, a technology with which a spurious due to a change in an output of the digital/analog converter can be suppressed. A low-pass filter is provided between an output side of a digital/analog converter and a variable attenuator to cut a frequency component corresponding to an overshoot generated when an output of the digital/analog converter is changed. Further, a period of time from when a control unit outputs a control voltage to when it reads a signal level detected by a detector is set to a period of time longer than a time constant of the low-pass filter determined by a cut-off frequency of the low-pass filter so that no influence is exerted on an operation of automatically controlling the signal level.

Abstract translation: 提供一种频率合成器，包括：设置在压控振荡器的后续级的可变衰减器; 检测器 以及控制单元，其根据检测电压输出用于经由数字/模拟转换器调整可变衰减器的衰减量的控制电压，由于数字/模拟转换器的输出的变化引起的寄生的杂散技术 被压制 在数字/模拟转换器的输出侧和可变衰减器之间提供低通滤波器，以便在数字/模拟转换器的输出改变时产生的过冲相应的剪切频率分量。 此外，从控制单元输出控制电压到读取检测器检测到的信号电平的时间段被设置为比由截止器确定的低通滤波器的时间常数更长的时间段 低通滤波器的频率，从而不会对自动控制信号电平的操作产生影响。

公开(公告)号：US10483983B2

公开(公告)日：2019-11-19

申请号：US15683788

申请日：2017-08-23

Applicant: NIHON DEMPA KOGYO CO., LTD.

Inventor： Tomoya Yorita ,  Shoichi Tsuchiya ,  Yasuo Kitayama

IPC: G06F1/10 ,  H03L1/02 ,  G06F1/08 ,  H03K21/10 ,  H03L7/18

Abstract: A clock generating circuit includes a dividing unit and a distribution unit. The dividing unit divides a reference clock to generate a divided clock, and the divided clock has a frequency of 1/N times of a frequency of the reference clock, where N is an integer of two or more. The distribution unit distributes the reference clock to a first route and a second route, the first route includes an output terminal that outputs a clock with a frequency identical to the frequency of the reference clock, and the second route includes the dividing unit. The dividing unit includes one or more amplifiers, one or more dividing circuits, and a correction circuit. The correction circuit is disposed between the amplifier and the dividing circuit, and the correction circuit corrects a level of an input clock input to the dividing circuit.