公开(公告)号：US20190245624A1

公开(公告)日：2019-08-08

申请号：US16343349

申请日：2017-10-16

申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION

发明人： Toshiki KISHI ,  Munehiko NAGATANI ,  Shinsuke NAKANO ,  Hiroaki KATSURAI ,  Masafumi NOGAWA ,  Hideyuki NOSAKA

IPC分类号： H04B10/50 ,  H04B10/572 ,  H01S5/0687 ,  H01S5/042 ,  H01S3/131

CPC分类号： H04B10/504 ,  H01S3/1317 ,  H01S5/042 ,  H01S5/0427 ,  H01S5/0687 ,  H03F1/22 ,  H03K19/0175 ,  H04B10/54 ,  H04B10/572

摘要： A driver circuit 11 includes a plurality of cascode-connected NMOS transistors, a modulating signal VGN1 is applied to a gate terminal of a lowermost stage transistor TN1 located at a lowermost stage out of the NMOS transistors, and an upper stage bias potential VGN2 that is a sum of a minimum gate-source voltage VGN1min and a maximum drain-source voltage VDS1max of a transistor (TN1) located immediately below an upper stage transistor located at an upper stage above the lowermost stage transistor of the NMOS transistors is applied to the upper stage transistor TN2.