Abstract:
A time division multiplex switching system for transmission of digital pulses from asynchronous pulse transmitters in which each incoming data stream is buffered until occurrence of an assigned time slot. During each such assigned time slot, a high speed clock subdivides the time slot into a plurality of subintervals during which data pulses and stuff pulses, as required, are transmitted through a switching matrix in a three level code. The data pulses are then detected, separated from the stuff pulses, and buffered. The original input pulse rate is regenerated and the data pulses are transmitted to the digital receivers at approximately such rate.