公开(公告)号：US11783795B1

公开(公告)日：2023-10-10

申请号：US17894122

申请日：2022-08-23

Applicant: NOVATEK Microelectronics Corp.

Inventor： Ying-Chieh Yen ,  Po-Chiang Hsu ,  Ching-Hao Lee ,  Cheng-Hsun Tsai

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2310/0291 ,  G09G2330/025 ,  G09G2330/06

Abstract: A gate driver for a panel, wherein the gate driver comprises at least an output channel unit, each of the output channel unit includes a first driving unit; a second driving unit; a first current limit circuit, coupled to the first driving unit, configured to control an output current according to an output voltage of the gate driver to limit an output current slew rate of the gate driver; and a second current limit circuit, coupled to the second driving unit, configured to control the output current according to the output voltage of the gate driver to limit the output current slew rate of the gate driver.