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1.发明申请公开(公告)号：US20190190315A1
公开(公告)日：2019-06-20
申请号：US16062635
申请日：2016-04-14
发明人： Zongguang XU , Jifeng WEN , Yong CHEN , Xiang LI , Yan LI , Yucan ZHAO , Ming YUAN , Qiang ZHOU , Guanghua LI , Tianen ZHAO , Dewen LI
CPC分类号： H02J13/0062 , G06F9/3877 , G06F11/1004 , H04L1/22
摘要： An apparatus and method for ensuring the reliability of a protection trip of an intelligent substation. The apparatus comprises a main CPU and an auxiliary CPU connected together, and a main FPGA and an auxiliary FPGA connected together, wherein the main FPGA and the auxiliary FPGA are both connected to a physical layer of a protection apparatus, and the main CPU and the auxiliary CPU are both connected to a state monitoring data output end of a protected device. Wherein, the main CPU sending a processing result to the main FPGA, the auxiliary CPU sending the processing result to the auxiliary FPGA, and the auxiliary FPGA synchronizing current information with the main FPGA after receiving information sent by the auxiliary CPU; and when the main FPGA receives trip information, the main FPGA comparing the consistency of current trip information obtained from the main CPU with that of current trip information obtained from the auxiliary FPGA, and if the two are consistent, the main FPGA sending the information received from the main CPU to the protection apparatus, otherwise, discarding the information received from the main CPU. An anti-misoperation ability of a protection apparatus is improved, and it is ensured that the apparatus cannot cause misoperation of primary device due to unknown errors when a hardware device failure, single event upset (SEU), etc. happens.
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