公开(公告)号：US20240406154A1

公开(公告)日：2024-12-05

申请号：US18528603

申请日：2023-12-04

Applicant: NVIDIA Corporation

Inventor： Miriam Menes ,  Naveen Cherukuri ,  Ahmad Atamli ,  Uria Basher ,  Mike Osborn ,  Mark Hummel ,  Liron Mula

IPC: H04L9/40

Abstract: Technologies for encrypting communication links between devices are described. A method includes generating a first initialization vector (IV), from a first subspace of IVs, for a first cryptographic ordered flow, and a second IV, from a second subspace of IVs that are mutually exclusive from the first subspace. The first and second cryptographic ordered flows share a key to secure multipath routing in a fabric between devices. The method sends, to the second device, a first packet for the first cryptographic ordered flow and a second packet for the second cryptographic ordered flow. The first packet includes a first security tag with the first IV and a first payload encrypted using the first IV and a first key. The second packet includes a second security tag with the second IV and a second payload encrypted using the second IV and a second key.

公开(公告)号：US20240231633A1

公开(公告)日：2024-07-11

申请号：US18592238

申请日：2024-02-29

Applicant: NVIDIA Corporation

Inventor： Shridhar Rasal ,  Oren Duer ,  Aviv Kfir ,  Liron Mula

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0611 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/067

Abstract: A system includes a hardware circuitry having a device coupled with one or more external memory devices. The device is to detect an input/output (I/O) request associated with an external memory device of the one or more external memory devices. The device is to record a first timestamp in response to detecting the I/O request transmitted to the external memory device. The device is further to detect an indication from the external memory device of a completion of the I/O request associated with the external memory device and record a second timestamp in response to detecting the indication. The device is also to determine a latency associated with the I/O request based on the first timestamp and the second timestamp.

公开(公告)号：US20230325089A1

公开(公告)日：2023-10-12

申请号：US17714575

申请日：2022-04-06

Applicant: NVIDIA Corporation

Inventor： Shridhar Rasal ,  Oren Duer ,  Aviv Kfir ,  Liron Mula

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0611 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/067

Abstract: A system includes a hardware circuitry having a device coupled with one or more external memory devices. The device is to detect an input/output (I/O) request associated with an external memory device of the one or more external memory devices. The device is to record a first timestamp in response to detecting the IO request transmitted to the external memory device. The device is further to detect an indication from the external memory device of a completion of the IO request associated with the external memory device and record a second timestamp in response to detecting the indication. The device is also to determine a latency associated with the IO request based on the first timestamp and the second timestamp.

公开(公告)号：US11947804B2

公开(公告)日：2024-04-02

申请号：US17714575

申请日：2022-04-06

Applicant: NVIDIA Corporation

Inventor： Shridhar Rasal ,  Oren Duer ,  Aviv Kfir ,  Liron Mula

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/00

CPC classification number: G06F3/0613 ,  G06F3/0611 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/067

Abstract: A system includes a hardware circuitry having a device coupled with one or more external memory devices. The device is to detect an input/output (I/O) request associated with an external memory device of the one or more external memory devices. The device is to record a first timestamp in response to detecting the IO request transmitted to the external memory device. The device is further to detect an indication from the external memory device of a completion of the IO request associated with the external memory device and record a second timestamp in response to detecting the indication. The device is also to determine a latency associated with the IO request based on the first timestamp and the second timestamp.