公开(公告)号：US12197272B2

公开(公告)日：2025-01-14

申请号：US17859352

申请日：2022-07-07

Applicant: NVIDIA Corporation

Inventor： Leon Lixingyu ,  Prosenjit Chatterjee ,  Anshu Nadkarni

IPC: G06F11/00 ,  G06F11/07

Abstract: A system includes a device having a controller a plurality of finite state machines (FSMs). The device is to detect that one or more FSMs of the plurality of FSMs fails to satisfy a non-idle duration criterion during an operation, where the one or more FSM that fail to satisfy the non-idle duration criterion are associated with one or more errors. The device is to determine a location of the one or more FSMs that fail to satisfy the non-idle duration criterion. The device is to record the location of the one or more FSMs and the one or more errors, restore the one or more FSM to an idle state, and transmit an indication that the one or more FSMs failed to satisfy the non-idle duration criterion.

公开(公告)号：US20240012705A1

公开(公告)日：2024-01-11

申请号：US17859352

申请日：2022-07-07

Applicant: NVIDIA Corporation

Inventor： Leon Lixingyu ,  Prosenjit Chatterjee ,  Anshu Nadkarni

IPC: G06F11/07

CPC classification number: G06F11/0769 ,  G06F11/0721

Abstract: A system includes a device having a controller a plurality of finite state machines (FSMs). The device is to detect that one or more FSMs of the plurality of FSMs fails to satisfy a non-idle duration criterion during an operation, where the one or more FSM that fail to satisfy the non-idle duration criterion are associated with one or more errors. The device is to determine a location of the one or more FSMs that fail to satisfy the non-idle duration criterion. The device is to record the location of the one or more FSMs and the one or more errors, restore the one or more FSM to an idle state, and transmit an indication that the one or more FSMs failed to satisfy the non-idle duration criterion.

公开(公告)号：US20250156260A1

公开(公告)日：2025-05-15

申请号：US19014072

申请日：2025-01-08

Applicant: NVIDIA Corporation

Inventor： Leon Lixingyu ,  Prosenjit Chatterjee ,  Anshu Nadkarni

IPC: G06F11/07

Abstract: A device includes a first finite state machine, and a controller coupled to the first finite state machine. The controller is to detect that the first finite state machine fails to perform a first operation within a first duration, and responsive to detecting that the first finite state machine fails to perform the first operation within the first duration, render the first finite state machine available to process a second operation by storing a reset value to a first register associated with the first finite state machine.