公开(公告)号：US20250028378A1

公开(公告)日：2025-01-23

申请号：US18222936

申请日：2023-07-17

Applicant: NVIDIA Corporation

Inventor： Ziyi Xu ,  Zheng Wu ,  Ben Pei En Tsai ,  Xuan Wang

IPC: G06F1/324 ,  H03L7/099

Abstract: Technologies directed to input current limiter (ICL) circuits with frequency control loops are described. One integrated circuit includes a processing core and an ICL circuit. The ICL circuit can limit an input current to the processing core within a current limit of the processing core. The ICL circuit can determine an input current and a supply voltage provided to the processing core at a first time. The ICL circuit can reduce a clock of the processing core from a first clock frequency to a second clock frequency with a linear frequency drop based on the current limit, the input current, and the supply voltage. value, the second value, and the third value. The first clock frequency corresponds to a first voltage, and the second frequency corresponds to a second voltage. The ICL circuit can reduce the clock to a third clock frequency corresponding to a third voltage.