公开(公告)号：US20240313754A1

公开(公告)日：2024-09-19

申请号：US18184117

申请日：2023-03-15

Applicant: NXP B.V.

Inventor： Shubham Ajaykumar Khandelwal ,  Gerard Villar Piqué

IPC: H03K5/24

CPC classification number: H03K5/2481

Abstract: A circuit that includes a voltage comparator for comparing two voltages. The comparator includes a first in series stage with a differential amplifier, a second in series stage with a differential amplifier, and one or more subsequent inverter stages. Each of the stages includes one or more switches for connecting the inputs of the comparison devices of the stages to their outputs during a precharge phase to charge capacitors with voltages based on the voltage thresholds of the comparison devices. In a subsequent comparison phase, the one or more switches are open, where a comparison between the two voltages is propagated through the stages.

公开(公告)号：US20240128866A1

公开(公告)日：2024-04-18

申请号：US18047053

申请日：2022-10-17

Applicant: NXP B.V.

Inventor： Gerard Villar Piqué ,  Shubham Ajaykumar Khandelwal ,  Ravichandra Karadi

IPC: H02M3/156 ,  H02M1/00

CPC classification number: H02M3/156 ,  H02M1/0025

Abstract: One example discloses a voltage converter, including: a power stage configured to generate an output voltage (Vo) and an output current (Jo) based on a switching frequency (fs); a primary control loop configured to vary the switching frequency (fs) in response to an on-time value code (Ton_code) and/or a peak output current code (iLpeak_code); and a secondary control loop configured to generate the Ton_code and/or the iLpeak_code.

公开(公告)号：US11601123B1

公开(公告)日：2023-03-07

申请号：US17523798

申请日：2021-11-10

Applicant: NXP B.V.

Inventor： Shubham Ajaykumar Khandelwal ,  Henricus Cornelis Johannes Büthker ,  Hendrik Johannes Bergveld

IPC: H03K17/22

Abstract: Embodiments of power-on reset (POR) circuits are described. In one embodiment, a POR circuit includes a primary ladder circuit connected to a supply voltage and configured to generate a reference signal for a reset signal in response to the supply voltage and a secondary ladder circuit connected to the supply voltage and configured to bias the primary ladder circuit in response to the supply voltage.