公开(公告)号：US09628062B1

公开(公告)日：2017-04-18

申请号：US15180092

申请日：2016-06-13

申请人： NXP B.V.

发明人： Van-Loi Le ,  Tae-Hyoung Kim ,  Juhui Li ,  Alan Yeow Khai Chang

IPC分类号： H03K3/289 ,  H03K5/19 ,  H03K3/3562

CPC分类号： H03K5/19 ,  H03K3/012 ,  H03K3/35625

摘要： A 24-transistor D flip-flop circuit operates in a sampling mode when a clock signal has a first voltage state, and a holding mode when the clock signal has a second voltage state. The flip-flop circuit includes an internal control node coupled to a reference voltage node by way of a transistor controllable to couple the internal control node to the reference voltage node when the clock signal has the second voltage state. The flip-flop has very low power dissipation as it includes a 4-transistor change-sense component to detect changes in input data. The change-sense component is coupled in series with the transistor and receives an indication of an input voltage state of the flip-flop circuit and an indication of an output voltage state of the flip-flop circuit, and inhibits toggling of the internal control node if the indicated input voltage state and the indicated output voltage state are the same.