公开(公告)号：US5758123A

公开(公告)日：1998-05-26

申请号：US420261

申请日：1995-04-11

申请人： Naoki Sano ,  Takeshi Yamamoto ,  Manabu Noriyasu ,  Satoru Natsui ,  Yuji Amano ,  Atsushi Ogasawara ,  Yuko Mizuta ,  Yoko Takihana

发明人： Naoki Sano ,  Takeshi Yamamoto ,  Manabu Noriyasu ,  Satoru Natsui ,  Yuji Amano ,  Atsushi Ogasawara ,  Yuko Mizuta ,  Yoko Takihana

IPC分类号： G06F17/50 ,  G06F9/455 ,  G06F3/00

CPC分类号： G06F17/5022

摘要： A verification support system wherein before a CPU mounted circuit is actually made such circuit model and an ICE model are made virtually and verification of such circuit model is performed using logic simulation on the ICE model; and when an error is found execution and verification up to the error point are omitted and are performed immediately after the error point to correct the error. A waveform, obtained by logic simulation, and a partially enlarged waveform thereof are displayed on different display regions for each time period and a display region is provided for saving a displayed waveform obtained when logic simulation is stopped. In another aspect of the invention, before an actual system is made by PLC, such PLC model is verified, and a test program is carried out to obtain verification when a process model is detached from the PLC model, and a sequence program is carried out by using a general purpose simulator with a debugging function. The verification system enhances efficiency of development of a CPU mounted circuit, and development of a sequence control system using a PLC.

摘要翻译： 一种验证支持系统，其中在实际制造CPU安装电路之前，虚拟地制造这样的电路模型和ICE模型，并且使用ICE模型上的逻辑模拟来执行这种电路模型的验证; 并且当发现错误时，省略错误点的执行和验证，并且在错误点之后立即执行以校正错误。 通过逻辑模拟获得的波形及其部分放大的波形在每个时间周期显示在不同的显示区域上，并且提供显示区域以保存当逻辑模拟停止时获得的显示波形。 在本发明的另一方面，在由PLC实际实现系统之前，验证了这种PLC模型，并且当过程模型与PLC模型分离时，执行测试程序以获得验证，并且执行顺控程序 通过使用具有调试功能的通用模拟器。 验证系统提高了CPU安装电路的开发效率，并开发了使用PLC的序列控制系统。

公开(公告)号：US5991533A

公开(公告)日：1999-11-23

申请号：US948992

申请日：1997-10-10

申请人： Naoki Sano ,  Takeshi Yamamoto ,  Manabu Noriyasu ,  Satoru Natsui ,  Yuji Amano ,  Atsushi Ogasawara ,  Yuko Mizuta ,  Yoko Takihana

发明人： Naoki Sano ,  Takeshi Yamamoto ,  Manabu Noriyasu ,  Satoru Natsui ,  Yuji Amano ,  Atsushi Ogasawara ,  Yuko Mizuta ,  Yoko Takihana

IPC分类号： G06F17/50 ,  G06F15/60

CPC分类号： G06F17/5022

摘要： A verification support system having the following characteristics: (1) Before actually making a CPU mounted circuit, virtually make a CPU mounted circuit model and an ICE model and perform verification of the CPU mounted circuit mode with logic simulation, by using the ICE model; (2) When an error is found in the verification of a program using logic simulation, the execution and verification of the steps up to one step before the error point is omitted and execution and verification are performed immediately from the error point, for the purpose of error correction; (3) A waveform obtained as a result of logic simulation and a partially enlarged waveform thereof are displayed on different display regions; (4) A display region for displaying a waveform obtained as a result of logic simulation every hour and a display region for saving a displayed waveform obtained when logic simulation is stopped, are provided separately; (5) When there are a plurality of target logic models, waveforms of logic simulation results are displayed on different display regions, respectively. The stop or restart of the renewing of waveforms can be performed individually or collectively; (6) Before making an actual system by PLC, virtually make a PLC model and a process model and verify the sequence program of the PLC; and (7) Prepare a test program for performing verification when a process model is detached from a PLC model, and verify a sequence program by using a general purpose simulator with a debugging function. The verification system enhances efficiency of development of a CPU mounted circuit, and development of a sequence control system using a PLC.

摘要翻译： 一种具有以下特点的验证支持系统：（1）在实际制作CPU安装电路之前，通过使用ICE模型，实际上使用CPU安装电路模型和ICE模型，并通过逻辑仿真执行CPU安装电路模式的验证; （2）在使用逻辑模拟的程序的验证中发现错误时，省略在错误点之前达到一步的步骤的执行和验证，并且从误差点立即执行和验证，为此目的 的纠错; （3）作为逻辑模拟得到的波形及其部分放大的波形显示在不同的显示区域上; （4）分别设置用于显示每小时作为逻辑模拟结果获得的波形的显示区域和用于保存逻辑模拟停止时获得的显示波形的显示区域; （5）当存在多个目标逻辑模型时，逻辑模拟结果的波形分别显示在不同的显示区域上。 停止或重新启动波形更新可单独或集体进行; （6）在通过PLC制作实际系统之前，先将PLC模型和过程模型进行实际仿真，验证PLC的顺控程序; 和（7）准备一个测试程序，以便在将过程模型与PLC模型分离时进行验证，并通过使用具有调试功能的通用模拟器验证序列程序。 验证系统提高了CPU安装电路的开发效率，并开发了使用PLC的序列控制系统。