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公开(公告)号：US20090212819A1
公开(公告)日：2009-08-27
申请号：US12037421
申请日：2008-02-26
CPC分类号： G06F17/505
摘要： A method for modifying an integrated circuit and integrated circuits are provided. The method includes: providing an integrated circuit design comprising a plurality of circuit books having a first threshold voltage; and replacing at least one of the plurality of circuit books with at least one gate array book having a second threshold voltage that is lower than the first threshold voltage.
摘要翻译： 提供了一种用于修改集成电路和集成电路的方法。 该方法包括：提供包括具有第一阈值电压的多个电路簿的集成电路设计; 以及用具有低于第一阈值电压的第二阈值电压的至少一个门阵列簿代替多个电路簿中的至少一个。
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公开(公告)号：US08103989B2
公开(公告)日：2012-01-24
申请号：US12037421
申请日：2008-02-26
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method for modifying an integrated circuit and integrated circuits are provided. The method includes: providing an integrated circuit design comprising a plurality of circuit books having a first threshold voltage; and replacing at least one of the plurality of circuit books with at least one gate array book having a second threshold voltage that is lower than the first threshold voltage.
摘要翻译： 提供了一种用于修改集成电路和集成电路的方法。 该方法包括：提供包括具有第一阈值电压的多个电路簿的集成电路设计; 以及用具有低于第一阈值电压的第二阈值电压的至少一个门阵列簿代替多个电路簿中的至少一个。
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3.发明授权公开(公告)号：US07752585B2
公开(公告)日：2010-07-06
申请号：US11872183
申请日：2007-10-15
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： Best and most recent NDR types are selected for all RLM's in a design in order to achieve timing closure. The selection employed uses two levels of filtering to examine the NDR types for each RLM, and based on the outcome of the filtering selects the most appropriate NDR type for input to the timing analysis. In one arrangement, the selection scheme is completely automated and is performed at the beginning of a timing analysis via script-driven processes.
摘要翻译： 为了实现定时关闭，所有RLM的设计都选择了最佳和最新的NDR类型。 所采用的选择使用两个级别的过滤来检查每个RLM的NDR类型，并且基于过滤的结果选择用于输入到时序分析的最适合的NDR类型。 在一种布置中，选择方案是完全自动化的，并且通过脚本驱动的过程在时序分析开始时执行。
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4.发明申请公开(公告)号：US20090100395A1
公开(公告)日：2009-04-16
申请号：US11872183
申请日：2007-10-15
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： Best and most recent NDR types are selected for all RLM's in a design in order to achieve timing closure. The selection employed uses two levels of filtering to examine the NDR types for each RLM, and based on the outcome of the filtering selects the most appropriate NDR type for input to the timing analysis. In one arrangement, the selection scheme is completely automated and is performed at the beginning of a timing analysis via script-driven processes.
摘要翻译： 为了实现定时关闭，所有RLM的设计都选择了最佳和最新的NDR类型。 所采用的选择使用两个级别的过滤来检查每个RLM的NDR类型，并且基于过滤的结果选择用于输入到时序分析的最适合的NDR类型。 在一种布置中，选择方案是完全自动化的，并且通过脚本驱动的过程在时序分析开始时执行。
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5.发明授权VLSI timing optimization with interleaved buffer insertion and wire sizing stages 失效具有交错缓冲器插入和线尺寸阶段的VLSI时序优化公开(公告)号：US07480886B2
公开(公告)日：2009-01-20
申请号：US11334256
申请日：2006-01-18
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5068
摘要： The invention relates to layout of circuit components, including determining the interconnections, buffers, or path nets between circuit blocks or circuit components and input/output bonding pads. This is accomplished by a method and program product that optimizes timing comprising. Wiring layout and buffer insertion is accomplished by setting all wires in the design to an initial best possible value, inserting buffers in longest nets of wires of the design, and degrading the resulting nets. This is accomplished by a wire sizing routine which takes the nets and degrades them accordingly. This degrading is done through a combination of one or more of knocking the wires down to lower levels and reducing their thickness. The amount of degradation is dependent on the final slack.
摘要翻译： 本发明涉及电路组件的布局，包括确定电路块或电路组件之间的互连，缓冲器或路径网以及输入/输出接合焊盘。 这是通过一种优化时序的方法和程序产品实现的，包括。 布线布局和缓冲区插入是通过将设计中的所有导线设置为初始的最佳可能值来实现的，将缓冲区插入设计中最长的网线，并降低所得的网络。 这是通过线网规则实现的，该规则采取网络并相应地降低它们。 这种降级是通过一种或多种将电线敲低到较低水平并减小其厚度的组合而完成的。 退化的量取决于最后的松弛。
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