公开(公告)号：US11531497B2

公开(公告)日：2022-12-20

申请号：US17166892

申请日：2021-02-03

Applicant: National Institute of Technology

Inventor： G. Lakshminarayanan ,  Antony Xavier Glittas ,  Mathini Sellathurai

IPC: G06F3/06 ,  G06F17/14

Abstract: The present invention discloses a data scheduling register tree structure for radix-2 FFT architecture. The operation method of the proposed invention, there is no need for the Random Access Memory (RAM) to store the data; instead, shift registers with some multiplexers are enough to perform the memory operation with less hardware. There are three steps in the FFT computation such as input storage, data processing and output retrieval. The data processing step is further configured in four different operations. The number of operation mainly depends upon the size of the FFT, which is equal to log2N modes. During each operation, the DSRT changes its structure and these structures are basically MDC (Multi-path Delay Commutator) structures.

公开(公告)号：US20210255804A1

公开(公告)日：2021-08-19

申请号：US17166892

申请日：2021-02-03

Applicant: National Institute of Technology

Inventor： G. Lakshminarayanan ,  Antony Xavier Glittas ,  Mathini Sellathurai

IPC: G06F3/06

Abstract: The present invention discloses a data scheduling register tree structure for radix-2 FFT architecture. The operation method of the proposed invention, there is no need for the Random Access Memory (RAM) to store the data; instead, shift registers with some multiplexers are enough to perform the memory operation with less hardware. There are three steps in the FFT computation such as input storage, data processing and output retrieval. The data processing step is further configured in four different operations. The number of operation mainly depends upon the size of the FFT, which is equal to log2N modes. During each operation, the DSRT changes its structure and these structures are basically MDC (Multi-path Delay Commutator) structures.