Adapting cache processing using phase libraries and real time simulators

    公开(公告)号:US11593271B2

    公开(公告)日:2023-02-28

    申请号:US17234031

    申请日:2021-04-19

    Applicant: NetApp, Inc.

    Abstract: A method, a computing device, and a non-transitory machine-readable medium for modifying cache settings in the array cache are provided. Cache settings are set in an array cache, such that the array cache caches data in an input/output (I/O) stream based on the cache settings. Multiple cache simulators simulate the caching the data from the I/O stream in the array cache using different cache settings in parallel with the array cache. The cache settings in the array cache are replaced with the cache settings from one of the cache simulators based on the determination that the cache simulators increase effectiveness of caching data in the array cache.

    Adapting Cache Processing Using Phase Libraries and Real Time Simulators

    公开(公告)号:US20210240630A1

    公开(公告)日:2021-08-05

    申请号:US17234031

    申请日:2021-04-19

    Applicant: NetApp, Inc.

    Abstract: A method, a computing device, and a non-transitory machine-readable medium for modifying cache settings in the array cache are provided. Cache settings are set in an array cache, such that the array cache caches data in an input/output (I/O) stream based on the cache settings, Multiple cache simulators simulate the caching the data from the I/O stream in the array cache using different cache settings in parallel with the array cache. The cache settings in the array cache are replaced with the cache settings from one of the cache simulators based on the determination that the cache simulators increase effectiveness of caching data in the array cache.

    Adapting cache processing using phase libraries and real time simulators

    公开(公告)号:US11003583B2

    公开(公告)日:2021-05-11

    申请号:US15496857

    申请日:2017-04-25

    Applicant: NetApp, Inc.

    Abstract: A method, a computing device, and a non-transitory machine-readable medium for modifying cache settings in the array cache are provided. Cache settings are set in an array cache, such that the array cache caches data in an input/output (I/O) stream based on the cache settings. Multiple cache simulators simulate the caching the data from the I/O stream in the array cache using different cache settings in parallel with the array cache. The cache settings in the array cache are replaced with the cache settings from one of the cache simulators based on the determination that the cache simulators increase effectiveness of caching data in the array cache.

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