PCIE ERROR REPORTING AND THROTTLING
    1.
    发明申请

    公开(公告)号:US20170091013A1

    公开(公告)日:2017-03-30

    申请号:US14868262

    申请日:2015-09-28

    Applicant: NetApp, Inc.

    CPC classification number: G06F11/0772 G06F11/0745 G06F11/076

    Abstract: Examples described herein include an error report throttling mechanism for Peripheral Component Interconnect Express (PCIe) systems. The throwing mechanism updates an interrupt for the first port, and selectively performs an interrupt routine, in response to detecting the error message, based at least in part on the interrupt count for the first port. For example, the throwing mechanism may compare the interrupt count with a reporting threshold to determine whether an error reporting limit has been exceeded for the first port. Upon determining that the error reporting limit has been reached, the throttling mechanism may disable the interrupt routine for subsequent error messages received at the first port.

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