公开(公告)号：US20140185593A1

公开(公告)日：2014-07-03

申请号：US14196804

申请日：2014-03-04

Applicant: NetLogic Microsystems, Inc.

Inventor： Yan WANG

IPC: H04L5/00

CPC classification number: H04L5/0058 ,  G06F3/00 ,  G06F9/46 ,  G06F13/14 ,  G06F13/3625 ,  G06F13/4031 ,  G06F15/17325

Abstract: A processing system includes an interchip interface that comprises an interchip interface module having an arbiter to allocate a dedicated time slice in every fixed number of time slices, to assign a first priority to store data item(s) from a first-type channel having a first datapath width in memory during the dedicated time slice. In the remaining time slices of the fixed number of time slices, the arbiter further arbitrates among multiple channels of one or more types other than a first type, where the multiple channels correspond to at least one datapath width different from the first datapath width, and channels with wider datapath win the arbitration. The arbiter further arbitrates among two or more channels of the same type if a certain type of channel(s) wins the arbitration in a time slice. A method for implementing the same is also disclosed.

Abstract translation: 一种处理系统包括芯片间接口，其包括具有仲裁器的芯片间接口模块，所述仲裁器在每个固定数量的时间片中分配专用时间片，以分配第一优先级以从具有 专用时间片内存储器中的第一个数据路径宽度。 在固定数量的时间片的剩余时间片中，仲裁器进一步在除第一类型之外的一种或多种类型的多个信道之中进行仲裁，其中多个信道对应于与第一数据路径宽度不同的至少一个数据路径宽度，以及 具有更广泛数据通路的通道赢得仲裁。 如果某种类型的信道在时间片中赢得仲裁，仲裁者将进一步仲裁相同类型的两个或多个信道。 还公开了其实现方法。