公开(公告)号：US07936018B2

公开(公告)日：2011-05-03

申请号：US12640565

申请日：2009-12-17

申请人： Nicolas Fourches

发明人： Nicolas Fourches

IPC分类号： H01L27/01

CPC分类号： H01L27/14689 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14679

摘要： A semiconductor device includes an active zone doped according to a first type; a drain zone formed in the active zone and doped according to a second type; a source zone formed in the active zone and doped according to the second type; an insulated gate zone separated from the active zone by an insulating layer; a deep well, doped according to the second type such that the active zone is located between the gate zone and the well; a floating gate zone formed in the active zone under a space existing between the drain zone and the source zone, the floating gate zone including defects introducing deep levels in the bandgap of the semiconductor material, the deep levels being suited to trap carriers corresponding to the first type such that a charge state of the floating gate zone is modified and a drain source current varies due to the presence of a supplementary potential on the floating gate zone, a concentration of defects in the floating gate zone being strictly greater than 1018 cm−3.

摘要翻译： 半导体器件包括根据第一类型掺杂的有源区; 形成在有源区中并根据第二类掺杂的漏区; 源区，形成在有源区并根据第二类掺杂; 通过绝缘层与有源区隔离的绝缘栅区; 深阱，根据第二类型掺杂，使得活性区位于栅极区和阱之间; 浮动栅极区，形成在存在于漏区和源极区之间的空间之下的有源区中，浮栅区包括在半导体材料的带隙中引入深层次的缺陷，所述深层适于捕获对应于 第一类型，使得浮栅区域的电荷状态被修改并且漏源电流由于在浮栅区域上存在辅助电位而变化，浮栅区域中的缺陷的浓度严格地大于1018cm- 3。

公开(公告)号：US20100155806A1

公开(公告)日：2010-06-24

申请号：US12640565

申请日：2009-12-17

申请人： Nicolas Fourches

发明人： Nicolas Fourches

IPC分类号： H01L29/788 ,  H01L21/265

CPC分类号： H01L27/14689 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14679

摘要： A semiconductor device includes an active zone doped according to a first type; a drain zone formed in the active zone and doped according to a second type; a source zone formed in the active zone and doped according to the second type; an insulated gate zone separated from the active zone by an insulating layer; a deep well, doped according to the second type such that the active zone is located between the gate zone and the well; a floating gate zone formed in the active zone under a space existing between the drain zone and the source zone, the floating gate zone including defects introducing deep levels in the bandgap of the semiconductor material, the deep levels being suited to trap carriers corresponding to the first type such that a charge state of the floating gate zone is modified and a drain source current varies due to the presence of a supplementary potential on the floating gate zone, a concentration of defects in the floating gate zone being strictly greater than 1018 cm−3.

摘要翻译： 半导体器件包括根据第一类型掺杂的有源区; 形成在有源区中并根据第二类掺杂的漏区; 源区，形成在有源区并根据第二类掺杂; 通过绝缘层与有源区隔离的绝缘栅区; 深阱，根据第二类型掺杂，使得活性区位于栅极区和阱之间; 浮动栅极区，形成在存在于漏区和源极区之间的空间之下的有源区中，浮栅区包括在半导体材料的带隙中引入深层次的缺陷，所述深层适于捕获对应于 第一类型，使得浮栅区域的电荷状态被修改并且漏源电流由于在浮栅区域上存在辅助电位而变化，浮栅区域中的缺陷的浓度严格地大于1018cm- 3。