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公开(公告)号：US07240303B1
公开(公告)日：2007-07-03
申请号：US10456768
申请日：2003-06-06
CPC分类号： G06F17/5022 , G01R31/31705 , G01R31/318364 , G06F11/3644
摘要： Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.
摘要翻译： 描述了硬件描述语言（HDL）级别的分析，诊断和调试制造硬件设计的技术和系统。 虽然硬件设计（HDL设计）已经在具有有限输入/输出引脚的集成电路产品中制造，但是这些技术和系统使集成电路产品中的硬件设计能够在HDL中进行全面分析，诊断和调试 水平速度。 以HDL级别调试硬件设计的能力有助于校正或调整硬件设计的HDL描述。
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2.发明授权Enhanced hardware debugging with embedded FPGAS in a hardware description language 有权通过硬件描述语言对嵌入式FPGAS进行增强的硬件调试公开(公告)号：US07827510B1
公开(公告)日：2010-11-02
申请号：US11809700
申请日：2007-05-31
CPC分类号： G06F17/5027
摘要： Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.
摘要翻译： 描述了硬件描述语言（HDL）级别的分析，诊断和调试制造硬件设计的技术和系统。 虽然硬件设计（HDL设计）已经在具有有限输入/输出引脚的集成电路产品中制造，但是这些技术和系统使集成电路产品中的硬件设计能够在HDL中进行全面分析，诊断和调试 水平速度。 以HDL级别调试硬件设计的能力有助于校正或调整硬件设计的HDL描述。
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公开(公告)号：US20080313579A1
公开(公告)日：2008-12-18
申请号：US12117711
申请日：2008-05-08
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： Various techniques related to clocking for use with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving descriptions of design circuitry including logic to receive input signals. The method further includes generating additional descriptions through at least one computer program including descriptions of a multiplexer to multiplex the input signals and delayed input signals, and provide them to the logic, and a demultiplexer to demultiplex output signals and delayed output signals from the logic. Other embodiments are described.
摘要翻译： 公开了与用于自动化电路设计和仿真的时钟有关的各种技术。 在一些实施例中，一种方法包括接收包括用于接收输入信号的逻辑的设计电路的描述。 该方法还包括通过至少一个计算机程序产生附加的描述，所述计算机程序包括多路复用器的描述，以复用输入信号和延迟的输入信号，并将其提供给逻辑，以及解复用器，用于从逻辑解复用输出信号和延迟的输出信号。 描述其他实施例。
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公开(公告)号：US07984400B2
公开(公告)日：2011-07-19
申请号：US12117705
申请日：2008-05-08
CPC分类号： G06F17/5027
摘要： Various techniques involving snapshots of the contents of registers are described and claimed. In some embodiments, a method includes receiving descriptions of design circuitry including design registers to receive register input signals. The method also includes generating additional descriptions through at least one computer program including descriptions of additional registers (snapshot registers) to receive snapshots of the register input signals, wherein the additional registers provide register initial condition signals for use in a simulation of at least a portion of the design circuitry. Other embodiments are described.
摘要翻译： 描述和要求保护涉及寄存器内容的快照的各种技术。 在一些实施例中，一种方法包括接收包括设计寄存器的设计电路的描述以接收寄存器输入信号。 该方法还包括通过包括用于接收寄存器输入信号的快照的附加寄存器（快照寄存器）的描述的至少一个计算机程序产生附加描述，其中附加寄存器提供用于模拟至少一部分的寄存器初始条件信号 的设计电路。 描述其他实施例。
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公开(公告)号：US20080313589A1
公开(公告)日：2008-12-18
申请号：US12117714
申请日：2008-05-08
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/62
摘要： Various techniques related to clocking signals used for automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving first and second asynchronous clock signals having a first phase relationship at a first time and sampling the second clock signal at transitions of the first clock. The method further includes storing the samples; and analyzing the samples to ascertain the first phase relationship of the second clock signal with respect to the first clock signal and provide a representation of the first phase relationship. Other embodiments are described.
摘要翻译： 公开了与用于自动化电路设计和模拟的时钟信号有关的各种技术。 在一些实施例中，一种方法包括在第一时间接收具有第一相位关系的第一和第二异步时钟信号，并且在第一时钟的转变处对第二时钟信号进行采样。 该方法还包括存储样品; 以及分析样本以确定第二时钟信号相对于第一时钟信号的第一相位关系，并提供第一相位关系的表示。 描述其他实施例。
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公开(公告)号：US08756557B2
公开(公告)日：2014-06-17
申请号：US12117693
申请日：2008-05-08
CPC分类号： G06F17/5022 , G06F17/5027
摘要： Various techniques for use in connection with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving initial condition signals from circuitry in a chip, and correlating values of at least some of the initial condition signals with objects in a hardware description language (HDL) used in simulation, wherein the HDL was used in describing at least some of the circuitry in the chip. Still other embodiments involve memory substitutions. Replicated circuitry may be in the same chip(s) are the design circuitry or a different chip(s). Still other embodiments are described.
摘要翻译： 公开了与自动化电路设计和仿真结合使用的各种技术。 在一些实施例中，一种方法包括从芯片中的电路接收初始条件信号，并将至少一些初始条件信号与在模拟中使用的硬件描述语言（HDL）中的对象相关联，其中HDL用于描述 芯片中的至少一些电路。 其他实施例涉及存储器替换。 复制电路可以在设计电路或不同芯片的同一芯片中。 还描述了其它实施例。
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公开(公告)号：US07908574B2
公开(公告)日：2011-03-15
申请号：US12117711
申请日：2008-05-08
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： Various techniques related to clocking for use with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving descriptions of design circuitry including logic to receive input signals. The method further includes generating additional descriptions through at least one computer program including descriptions of a multiplexer to multiplex the input signals and delayed input signals, and provide them to the logic, and a demultiplexer to demultiplex output signals and delayed output signals from the logic. Other embodiments are described.
摘要翻译： 公开了与用于自动化电路设计和仿真的时钟有关的各种技术。 在一些实施例中，一种方法包括接收包括用于接收输入信号的逻辑的设计电路的描述。 该方法还包括通过至少一个计算机程序产生附加的描述，所述计算机程序包括多路复用器的描述，以复用输入信号和延迟的输入信号，并将其提供给逻辑，以及解复用器，用于从逻辑解复用输出信号和延迟的输出信号。 描述其他实施例。
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8.发明授权Method and apparatus for determining a phase relationship between asynchronous clock signals 有权用于确定异步时钟信号之间的相位关系的方法和装置公开(公告)号：US07904859B2
公开(公告)日：2011-03-08
申请号：US12117714
申请日：2008-05-08
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/62
摘要： Various techniques related to clocking signals used for automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving first and second asynchronous clock signals having a first phase relationship at a first time, and sampling the second clock signal at transitions of the first clock. The method further includes storing the samples; and analyzing the samples to ascertain the first phase relationship of the second clock signal with respect to the first clock signal and provide a representation of the first phase relationship. Other embodiments are described.
摘要翻译： 公开了与用于自动化电路设计和模拟的时钟信号有关的各种技术。 在一些实施例中，一种方法包括在第一时间接收具有第一相位关系的第一和第二异步时钟信号，以及在第一时钟的转变时采样第二时钟信号。 该方法还包括存储样品; 以及分析样本以确定第二时钟信号相对于第一时钟信号的第一相位关系，并提供第一相位关系的表示。 描述其他实施例。
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公开(公告)号：US20080313578A1
公开(公告)日：2008-12-18
申请号：US12117705
申请日：2008-05-08
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： Various techniques involving snapshots of the contents of registers are described and claimed. In some embodiments, a method includes receiving descriptions of design circuitry including design registers to receive register input signals. The method also includes generating additional descriptions through at least one computer program including descriptions of additional registers (snapshot registers) to receive snapshots of the register input signals, wherein the additional registers provide register initial condition signals for use in a simulation of at least a portion of the design circuitry. Other embodiments are described.
摘要翻译： 描述和要求保护涉及寄存器内容的快照的各种技术。 在一些实施例中，一种方法包括接收包括设计寄存器的设计电路的描述以接收寄存器输入信号。 该方法还包括通过包括用于接收寄存器输入信号的快照的附加寄存器（快照寄存器）的描述的至少一个计算机程序产生附加描述，其中附加寄存器提供用于模拟至少一部分的寄存器初始条件信号 的设计电路。 描述其他实施例。
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公开(公告)号：US20080301601A1
公开(公告)日：2008-12-04
申请号：US12117693
申请日：2008-05-08
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5027
摘要： Various techniques for use in connection with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving initial condition signals from circuitry in a chip, and correlating values of at least some of the initial condition signals with objects in a hardware description language (HDL) used in simulation, wherein the HDL was used in describing at least some of the circuitry in the chip. Still other embodiments involve memory substitutions. Replicated circuitry may be in the same chip(s) are the design circuitry or a different chip(s). Still other embodiments are described.
摘要翻译： 公开了与自动化电路设计和仿真结合使用的各种技术。 在一些实施例中，一种方法包括从芯片中的电路接收初始条件信号，并将至少一些初始条件信号与在模拟中使用的硬件描述语言（HDL）中的对象相关联，其中HDL用于描述 芯片中的至少一些电路。 其他实施例涉及存储器替换。 复制电路可以在设计电路或不同芯片的同一芯片中。 还描述了其它实施例。
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