公开(公告)号：US20240187101A1

公开(公告)日：2024-06-06

申请号：US18060817

申请日：2022-12-01

Applicant: Nokia Solutions and Networks Oy

Inventor： Doutje VAN VEEN ,  Vincent HOUTSMA

IPC: H04B10/516 ,  H04B10/079 ,  H04L1/00 ,  H04Q11/00

CPC classification number: H04B10/5161 ,  H04B10/07953 ,  H04L1/0003 ,  H04L1/0032 ,  H04L1/0042 ,  H04Q11/0067 ,  H04Q2011/0088

Abstract: A network element includes at least one processor and at least one memory. The at least one non-transitory memory including computer program code configured to, when executed by the at least one processor, cause the apparatus to determine whether a bit error rate (BER) of a FEC codeword is at or below a correctable BER, wherein the FEC codeword is transmitted between an OLT and ONU, a first percentage of the FEC codeword is at a lower order modulation, and a second percentage of the FEC codeword is at a higher order modulation, establish, based on a determination that the BER is at or below the correctable BER, a connection between the OLT and the ONU at the higher order modulation, and maintain, based on a determination that the BER is greater than the correctable BER, the connection between the OLT and the ONU at the lower order modulation.