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    System for suspending current bus cycle of microprocessor upon receiving external bus retry signal for executing other process and re-staring the suspended bus cycle thereafter
    1.
    发明授权
    System for suspending current bus cycle of microprocessor upon receiving external bus retry signal for executing other process and re-staring the suspended bus cycle thereafter 有权
    系统暂停当前总线周期的微处理器接收外部总线重试信号执行其他过程，并重新启动暂停的总线周期

    公开(公告)号：US06735713B1

    公开(公告)日：2004-05-11

    申请号：US09521544

    申请日：2000-03-09

    申请人： Norio Fujita ,  Mashahiro Murakami ,  Yoshifumi Sakamoto

    发明人： Norio Fujita ,  Mashahiro Murakami ,  Yoshifumi Sakamoto

    IPC分类号： G06F104

    CPC分类号： G06F13/405

    摘要： The present invention is directed to a microprocessor (MPU) 10 comprising a bridge chip 12 including a bus retry output part (40) for outputting a bus retry (BRTY) signal; a bus retry detection part (30) for determining whether a bus retry signal is input from the bridge chip 12; and a bus cycle controller (38) for suspending a currently executed bus cycle in response to detection of the bus retry signal and for re-starting the suspended bus cycle. The bridge chip also preferably includes an interrupt detection part (32) for determining whether another process request is issued during suspension of the bus cycle; and an interrupt controller (38) for executing that other process before re-starting the suspended bus cycle.

    摘要翻译： 本发明涉及一种微处理器（MPU）10，其包括桥接芯片12，桥接芯片12包括用于输出总线重试（BRTY）信号的总线重试输出部分（40） 用于确定总线重试信号是否从桥芯片12输入的总线重试检测部分（30）; 以及一个总线周期控制器（38），用于响应于总线重试信号的检测和暂停总线周期重新启动暂停当前执行的总线周期。 桥接芯片还优选地包括用于在暂停总线周期期间确定是否发出另一个处理请求的中断检测部分（32） 以及用于在重新启动暂停的总线周期之前执行该另一进程的中断控制器（38）。