公开(公告)号：US12236332B2

公开(公告)日：2025-02-25

申请号：US17743473

申请日：2022-05-13

Applicant: Novatek Microelectronics Corp.

Inventor： Chien Te Tung ,  Jen-Wei Liang ,  Chih Feng Juan

IPC: G06N3/04 ,  G06F7/499 ,  G06F15/78 ,  G11C7/10

Abstract: A compute-in-memory (CIM) macro device and an electronic device are proposed. The CIM macro device includes a CIM cell array including multiple CIM cells. First data is being divided into at least two bit groups including a first bit group which is the most significant bits of the first data and a second bit group which is the least significant bits of the first data, and the bit groups are respectively loaded in CIM cells of different columns of the CIM cell array. The electronic device includes at least one CIM macro and at least one processing circuit. The processing circuit is configured to receive and perform operation on parallel outputs respectively corresponding to the columns of the CIM cell array, where the parallel outputs include multiple correspondences, and where each of the correspondences includes most significant bits of an output activation and least significant bits of the output activation.

公开(公告)号：US20220366947A1

公开(公告)日：2022-11-17

申请号：US17743473

申请日：2022-05-13

Applicant: Novatek Microelectronics Corp.

Inventor： Chien Te Tung ,  Jen-Wei Liang ,  Chih Feng Juan

IPC: G11C7/10 ,  G06F7/499

Abstract: A compute-in-memory (CIM) macro device and an electronic device are proposed. The CIM macro device includes a CIM cell array including multiple CIM cells. First data is being divided into at least two bit groups including a first bit group which is the most significant bits of the first data and a second bit group which is the least significant bits of the first data, and the bit groups are respectively loaded in CIM cells of different columns of the CIM cell array. The electronic device includes at least one CIM macro and at least one processing circuit. The processing circuit is configured to receive and perform operation on parallel outputs respectively corresponding to the columns of the CIM cell array, where the parallel outputs include multiple correspondences, and where each of the correspondences includes most significant bits of an output activation and least significant bits of the output activation.

公开(公告)号：US20220366216A1

公开(公告)日：2022-11-17

申请号：US17743476

申请日：2022-05-13

Applicant: Novatek Microelectronics Corp.

Inventor： Chien Te Tung ,  Chih Feng Juan ,  Jen-Wei Liang

IPC: G06N3/04 ,  G06F15/78

Abstract: A method and a non-transitory computer readable medium for CIM arrangement, and an electronic device applying the same are proposed. The method for CIM arrangement includes to obtain information of the number of CIM macros and information of the dimension of each of the CIM micros, to obtain information of the number of input channels and the number of output channels of a designated convolutional layer of a designate neural network, and to determine a CIM macro arrangement for arranging the CIM macros according to the number of the CIM macros, the dimension of each of the CIM macros, the number of the input channels and the number of the output channels of the designated convolutional layer of the designated neural network, for applying convolution operation to the input channels to generate the output channels.