公开(公告)号：US08966192B2

公开(公告)日：2015-02-24

申请号：US13912239

申请日：2013-06-07

Applicant: Novatek Microelectronics Corp.

Inventor： Te-Lin Ping ,  I-Huan Huang

IPC: G06F12/00

CPC classification number: G06F12/00

Abstract: A memory control system includes a first queue unit, a second queue unit, a first transforming unit, a second transforming unit, an arbiter and a control unit. The first queue unit temporarily stores multiple first request instructions. The second queue unit temporarily stores multiple second request instructions. The first transforming unit selectively re-assigns memory addresses corresponding to these first request instructions. The second transforming unit selectively re-assigns memory addresses corresponding to these second request instructions. The arbiter performs immediate scheduling of the one or more first request instructions and the one or more second request instructions to the memory. The control unit compares bandwidths of the one or more first request instructions with bandwidths of the one or more second request instructions, and controls the first transforming unit and the second transforming unit to perform re-assigning operations or not according to compared results.

Abstract translation: 存储器控制系统包括第一队列单元，第二队列单元，第一变换单元，第二变换单元，仲裁器和控制单元。 第一队列单元临时存储多个第一请求指令。 第二队列单元临时存储多个第二请求指令。 第一变换单元选择性地重新分配对应于这些第一请求指令的存储器地址。 第二变换单元选择性地重新分配对应于这些第二请求指令的存储器地址。 仲裁器将一个或多个第一请求指令和一个或多个第二请求指令立即调度到存储器。 控制单元将一个或多个第一请求指令的带宽与一个或多个第二请求指令的带宽进行比较，并且根据比较结果控制第一变换单元和第二变换单元执行重新分配操作。