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公开(公告)号：US11789072B2
公开(公告)日：2023-10-17
申请号：US17947641
申请日：2022-09-19
发明人： Wei-Ling Lin
IPC分类号： H03K5/00 , G01R31/317 , H03K21/08 , H03K5/19
CPC分类号： G01R31/31727 , H03K5/19 , H03K21/08
摘要： A clock monitor circuit includes a monitor and a tunable counter. The monitor can monitor a clock under test. The tunable counter can count an integer according to a reference clock and set a target number. If a stable signal relative to the clock under test is toggled, the tunable counter can switch the target number from a large number to a small number. The tunable counter can perform an automatic detection process, so as to transmit a check signal to the monitor. In response to the check signal, if the clock under test is undetectable, the monitor will not transmit any confirmation signal back to the tunable counter, and the tunable counter will gradually increase the integer. When the integer is equal to the target number, the tunable counter generates a failure signal.
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公开(公告)号：US10742203B2
公开(公告)日：2020-08-11
申请号：US16515316
申请日：2019-07-18
发明人： Wei-Ling Lin
摘要： A delay line circuit with a calibration function, includes N delay modules and a calibration module. The N delay modules are serially coupled to each other. The calibration module generates a calibration start signal and a calibration stop signal according to a calibration signal and a clock signal, and the calibration start signal is outputted to the N delay modules, so that the N delay modules output N delay signals according to N control signals and the calibration start signal. The calibration module calibrates the N control signals according to the N delay signals and the calibration stop signal, so that the N delay modules generate N calibrated delay signals according to the N calibrated control signals and the clock signal. A generation time instant of the calibration stop signal is later than a generation time instant of the calibration start signal.
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