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    USING A HARDWARE SEQUENCER IN A DIRECT MEMORY ACCESS SYSTEM OF A SYSTEM ON A CHIP
    1.
    发明申请
    USING A HARDWARE SEQUENCER IN A DIRECT MEMORY ACCESS SYSTEM OF A SYSTEM ON A CHIP 有权

    公开(公告)号：US20250103529A1

    公开(公告)日：2025-03-27

    申请号：US18970570

    申请日：2024-12-05

    Applicant: NVIDIA Corporation

    Inventor： Ahmad Itani ,  Yen-Te Shih ,  Jagadeesh Sankaran ,  Ravi P. Singh ,  Ching-Yu Hung

    IPC: G06F13/28

    Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

    SIMD DATA PATH ORGANIZATION TO INCREASE PROCESSING THROUGHPUT IN A SYSTEM ON A CHIP
    3.
    发明申请
    SIMD DATA PATH ORGANIZATION TO INCREASE PROCESSING THROUGHPUT IN A SYSTEM ON A CHIP 有权

    公开(公告)号：US20230050062A1

    公开(公告)日：2023-02-16

    申请号：US17391395

    申请日：2021-08-02

    Applicant: NVIDIA Corporation

    Inventor： Ching-Yu Hung ,  Ravi P. Singh ,  Jagadeesh Sankaran ,  Yen-Te Shih ,  Ahmad Itani

    IPC: G06F9/30 ,  G06F9/38

    Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

    USING A VECTOR PROCESSOR TO CONFIGURE A DIRECT MEMORY ACCESS SYSTEM FOR FEATURE TRACKING OPERATIONS IN A SYSTEM ON A CHIP
    4.
    发明申请
    USING A VECTOR PROCESSOR TO CONFIGURE A DIRECT MEMORY ACCESS SYSTEM FOR FEATURE TRACKING OPERATIONS IN A SYSTEM ON A CHIP 有权

    公开(公告)号：US20230048836A1

    公开(公告)日：2023-02-16

    申请号：US17391875

    申请日：2021-08-02

    Applicant: NVIDIA Corporation

    Inventor： Ahmad Itani ,  Yen-Te Shih ,  Jagadeesh Sankaran ,  Ravi P Singh ,  Ching-Yu Hung

    IPC: G06F9/30 ,  G06F15/80 ,  G06F13/28

    Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

    USING A HARDWARE SEQUENCER IN A DIRECT MEMORY ACCESS SYSTEM OF A SYSTEM ON A CHIP
    5.
    发明申请
    USING A HARDWARE SEQUENCER IN A DIRECT MEMORY ACCESS SYSTEM OF A SYSTEM ON A CHIP 有权

    公开(公告)号：US20230042226A1

    公开(公告)日：2023-02-09

    申请号：US17391867

    申请日：2021-08-02

    Applicant: NVIDIA Corporation

    Inventor： Ahmad Itani ,  Yen-Te Shih ,  Jagadeesh Sankaran ,  Ravi P. Singh ,  Ching-Yu Hung

    IPC: G06F13/28

    Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

    Performing load and store operations of 2D arrays in a single cycle in a system on a chip
    6.
    发明授权
    Performing load and store operations of 2D arrays in a single cycle in a system on a chip 有权

    公开(公告)号：US12099439B2

    公开(公告)日：2024-09-24

    申请号：US17391468

    申请日：2021-08-02

    Applicant: NVIDIA Corporation

    Inventor： Ching-Yu Hung ,  Ravi P Singh ,  Jagadeesh Sankaran ,  Yen-Te Shih ,  Ahmad Itani

    IPC: G06F12/1081 ,  G06F9/30 ,  G06F12/02 ,  G06F13/28

    CPC classification number: G06F12/0238 ,  G06F9/30043 ,  G06F12/1081 ,  G06F13/28

    Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

    Reduced memory write requirements in a system on a chip using automatic store predication
    7.
    发明授权
    Reduced memory write requirements in a system on a chip using automatic store predication 有权

    公开(公告)号：US11954496B2

    公开(公告)日：2024-04-09

    申请号：US17391374

    申请日：2021-08-02

    Applicant: NVIDIA Corporation

    Inventor： Ching-Yu Hung ,  Ravi P Singh ,  Jagadeesh Sankaran ,  Yen-Te Shih ,  Ahmad Itani

    IPC: G06F9/38

    CPC classification number: G06F9/3887 ,  G06F9/38585

    Abstract: In various examples, systems and methods for reducing written requirements in a system on chip (SoC) are described herein. For instance, a total number of iterations may be determined for processing data, such as data representing an array. In some circumstances, a set of iterations may include a first number of iterations that is less than a second number of iterations. As such, and during execution of the set of iterations, a predicate flag corresponding to an excess iteration of the set of iterations may be generated, where the excess iteration corresponds to an iteration that is part of a number of excess iterations that is associated with a difference between the first number of iterations and the second number of iterations. Based on the predicate flag, one or more first values corresponding to the iteration may be prevented from being written to memory.

    Accelerating table lookups using a decoupled lookup table accelerator in a system on a chip
    8.
    发明授权
    Accelerating table lookups using a decoupled lookup table accelerator in a system on a chip 有权

    公开(公告)号：US11836527B2

    公开(公告)日：2023-12-05

    申请号：US17391369

    申请日：2021-08-02

    Applicant: NVIDIA Corporation

    Inventor： Ravi P Singh ,  Ching-Yu Hung ,  Jagadeesh Sankaran ,  Ahmad Itani ,  Yen-Te Shih

    IPC: G06F9/50 ,  G06F7/76 ,  G06F1/03

    CPC classification number: G06F9/5027 ,  G06F1/03 ,  G06F7/76 ,  G06F9/5077

    Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

    USING PER MEMORY BANK LOAD CACHES FOR REDUCING POWER USE IN A SYSTEM ON A CHIP
    9.
    发明申请
    USING PER MEMORY BANK LOAD CACHES FOR REDUCING POWER USE IN A SYSTEM ON A CHIP 有权

    公开(公告)号：US20230124604A1

    公开(公告)日：2023-04-20

    申请号：US18069722

    申请日：2022-12-21

    Applicant: NVIDIA Corporation

    Inventor： Ching-Yu Hung ,  Ravi P Singh ,  Jagadeesh Sankaran ,  Yen-Te Shih ,  Ahmad Itani

    IPC: G06F3/06 ,  G06F12/0802

    Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

    REDUCED MEMORY WRITE REQUIREMENTS IN A SYSTEM ON A CHIP USING AUTOMATIC STORE PREDICATION
    10.
    发明申请
    REDUCED MEMORY WRITE REQUIREMENTS IN A SYSTEM ON A CHIP USING AUTOMATIC STORE PREDICATION 有权

    公开(公告)号：US20230049442A1

    公开(公告)日：2023-02-16

    申请号：US17391374

    申请日：2021-08-02

    Applicant: NVIDIA Corporation

    Inventor： Ching-Yu Hung ,  Ravi P. Singh ,  Jagadeesh Sankaran ,  Yen-Te Shih ,  Ahmad Itani

    IPC: G06F9/38 ,  G06F9/30 ,  G06F9/455

    Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

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