公开(公告)号：US10719451B2

公开(公告)日：2020-07-21

申请号：US15868513

申请日：2018-01-11

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： Mayan Moudgill ,  A. Joseph Hoane ,  Lei Wang ,  Gary Nacer ,  Aaron G. Milbury ,  Enrique A. Barria ,  Paul Hurtley

IPC: G06F12/1027 ,  G06F12/1036 ,  G06F12/1009 ,  G06F12/0864

Abstract: A processor includes a translation lookaside buffer (TLB) comprising a plurality of ways, wherein each way is associated with a respective page size, and a processing core, communicatively coupled to the TLB, to execute an instruction associated with a virtual memory page, identify a first way of the plurality of ways, wherein the first way is associated with a first page size, determine an index value using the virtual memory page and the first page size for the first way, determine, using the index value, a first TLB entry of the first way, and translate, using a memory address translation stored in the first TLB entry, the first virtual memory page to a first physical memory page.

公开(公告)号：US20180203806A1

公开(公告)日：2018-07-19

申请号：US15868513

申请日：2018-01-11

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： Mayan Moudgill ,  A. Joseph Hoane ,  Lei Wang ,  Gary Nacer ,  Aaron G. Milbury ,  Enrique A. Barria ,  Paul Hurtley

IPC: G06F12/1027 ,  G06F12/1009

Abstract: A processor includes a translation lookaside buffer (TLB) comprising a plurality of ways, wherein each way is associated with a respective page size, and a processing core, communicatively coupled to the TLB, to execute an instruction associated with a virtual memory page, identify a first way of the plurality of ways, wherein the first way is associated with a first page size, determine an index value using the virtual memory page and the first page size for the first way, determine, using the index value, a first TLB entry of the first way, and translate, using a memory address translation stored in the first TLB entry, the first virtual memory page to a first physical memory page.