ASSYMETRIC ALLOCATION OF SRAM AND DATA LAYOUT FOR EFFICIENT MATRIX MULTIPLICATION

    公开(公告)号:US20190095399A1

    公开(公告)日:2019-03-28

    申请号:US15716225

    申请日:2017-09-26

    Abstract: Techniques are described herein for performing efficient matrix multiplication in architectures with scratchpad memories or associative caches using asymmetric allocation of space for the different matrices. The system receives a left matrix and a right matrix. In an embodiment, the system allocates, in a scratchpad memory, asymmetric memory space for tiles for each of the two matrices as well as a dot product matrix. The system proceeds with then performing dot product matrix multiplication involving the tiles of the left and the right matrices, storing resulting dot product values in corresponding allocated dot product matrix tiles. The system then proceeds to write the stored dot product values from the scratchpad memory into main memory.

    Assymetric allocation of SRAM and data layout for efficient matrix multiplication

    公开(公告)号:US11138291B2

    公开(公告)日:2021-10-05

    申请号:US15716225

    申请日:2017-09-26

    Abstract: Techniques are described herein for performing efficient matrix multiplication in architectures with scratchpad memories or associative caches using asymmetric allocation of space for the different matrices. The system receives a left matrix and a right matrix. In an embodiment, the system allocates, in a scratchpad memory, asymmetric memory space for tiles for each of the two matrices as well as a dot product matrix. The system proceeds with then performing dot product matrix multiplication involving the tiles of the left and the right matrices, storing resulting dot product values in corresponding allocated dot product matrix tiles. The system then proceeds to write the stored dot product values from the scratchpad memory into main memory.

    ASYMMETRIC ALLOCATION OF SRAM AND DATA LAYOUT FOR EFFICIENT MATRIX-MATRIX MULTIPLICATION

    公开(公告)号:US20210312014A1

    公开(公告)日:2021-10-07

    申请号:US17349817

    申请日:2021-06-16

    Abstract: Techniques are described herein for performing efficient matrix multiplication in architectures with scratchpad memories or associative caches using asymmetric allocation of space for the different matrices. The system receives a left matrix and a right matrix. In an embodiment, the system allocates, in a scratchpad memory, asymmetric memory space for tiles for each of the two matrices as well as a dot product matrix. The system proceeds with then performing dot product matrix multiplication involving the tiles of the left and the right matrices, storing resulting dot product values in corresponding allocated dot product matrix tiles. The system then proceeds to write the stored dot product values from the scratchpad memory into main memory.

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