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公开(公告)号：US20220187665A1
公开(公告)日：2022-06-16
申请号：US17485297
申请日：2021-09-24
发明人： Zhenhong XIAO , Peng LIU , Chao LIANG , Aiyu DING , Yongqiang ZHANG , Jingyi XU , Hui YUAN , Jiantao LIU
IPC分类号： G02F1/1362 , H01L27/12 , G02F1/1345 , G02F1/1333 , G06F3/041
摘要： The present disclosure provides an array substrate and a display panel. The array substrate includes a base substrate and at least one signal line unit in a fan-out region of the base substrate. Each of the at least one signal line unit includes two first signal lines and one second signal line, and the two first signal lines and the one second signal line are respectively in different layers and extend in a same direction. A center line of an orthographic projection of the one second signal line on the base substrate overlaps with a center line of an orthographic projection of an interval region between the two first signal lines.
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公开(公告)号：US20240353720A1
公开(公告)日：2024-10-24
申请号：US18028523
申请日：2022-03-31
发明人： Peirong HUO , Chao LIANG , Peng LIU , Jingyi XU , Bo LI , Zhenhong XIAO
IPC分类号： G02F1/1362
CPC分类号： G02F1/136286 , G02F1/136218
摘要： An array substrate and a display device are provided. The array substrate includes a display area and a non-display area that at least partially surrounds the display area; the non-display area includes at least two clock signal lines, wherein a ratio of a spacing between two adjacent clock signal lines to a line width of the clock signal lines is greater than or equal to 3.
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公开(公告)号：US20240355834A1
公开(公告)日：2024-10-24
申请号：US18688049
申请日：2022-07-28
发明人： Bo HUANG , Jianyun XIE , Jingyi XU , Hong LIU , Yongqiang ZHANG , Shuai HAN , Zhenhong XIAO , Pengyu ZHAO , Hao WANG , Wanzhi CHEN
IPC分类号： H01L27/12
CPC分类号： H01L27/124 , H01L27/1222
摘要： A display substrate, a display panel, and a display apparatus. The display substrate includes a base substrate; a gate line extending in a first direction on the base substrate; and a transistor located on the base substrate, where the transistor includes a gate electrode and a first electrode that is located at a side of a layer where the gate electrode is located away from the base substrate, part of the gate line is used as the gate electrode, an orthogonal projection of the gate electrode on the base substrate in a second direction is located within an orthogonal projection of the first electrode on the base substrate in the second direction, and the second direction intersects with the first direction.
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