公开(公告)号：US20100162187A1

公开(公告)日：2010-06-24

申请号：US12370065

申请日：2009-02-12

申请人： Paul Penzes ,  Koen Lampaert

发明人： Paul Penzes ,  Koen Lampaert

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H01L27/0207 ,  H01L27/11807

摘要： A mixed-height cell library for designing integrated circuits is provided. The mixed-height cell library includes a first plurality of cells having a first track height and a second plurality of cells having a second track height that are configured to be coupled to the first plurality of cells at respective power and ground rail lines. A method for mixed-height cell placement and optimization is also provided. The method comprises abutting cells of different track heights to form a plurality of rows of cells by coupling power and ground rails of the cells at a secondary layer that is different from a primary layer that is used to connect active material and determining whether re-ordering cells within rows allows for further compaction of adjacent rows. The method further comprises re-ordering cells within rows so to allow for further compaction of adjacent rows. The method also includes the steps of splitting rows vertically to minimize the distance between the split rows.

摘要翻译： 提供了用于设计集成电路的混合高度单元库。 混合高度单元库包括具有第一轨道高度的第一多个单元和具有第二轨道高度的第二多个单元，其被配置为在相应的电源和地面轨线处耦合到第一多个单元。 还提供了一种混合高度单元放置和优化的方法。 该方法包括通过在不同于用于连接活性材料的主层的次级层处耦合电池的功率和接地轨，来形成不同轨道高度的单元以形成多行单元，并确定是否重新排序 行内的单元允许相邻行的进一步压缩。 该方法还包括重新排序行内的单元，以允许相邻行的进一步压缩。 该方法还包括垂直分割行以最小化分割行之间的距离的步骤。

公开(公告)号：US08276109B2

公开(公告)日：2012-09-25

申请号：US12370065

申请日：2009-02-12

申请人： Paul Penzes ,  Koen Lampaert

发明人： Paul Penzes ,  Koen Lampaert

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H01L27/0207 ,  H01L27/11807

摘要： A mixed-height cell library for designing integrated circuits is provided. The mixed-height cell library includes a first plurality of cells having a first track height and a second plurality of cells having a second track height that are configured to be coupled to the first plurality of cells at respective power and ground rail lines. A method for mixed-height cell placement and optimization is also provided. The method comprises abutting cells of different track heights to form a plurality of rows of cells by coupling power and ground rails of the cells at a secondary layer that is different from a primary layer that is used to connect active material and determining whether re-ordering cells within rows allows for further compaction of adjacent rows. The method further comprises re-ordering cells within rows so to allow for further compaction of adjacent rows. The method also includes the steps of splitting rows vertically to minimize the distance between the split rows.

摘要翻译： 提供了一种用于设计集成电路的混合高度单元库。 混合高度单元库包括具有第一轨道高度的第一多个单元和具有第二轨道高度的第二多个单元，其被配置为在相应的电源和地面轨线处耦合到第一多个单元。 还提供了一种混合高度单元放置和优化的方法。 该方法包括通过在不同于用于连接活性材料的主层的次级层处耦合电池的功率和接地轨，来形成不同轨道高度的单元以形成多行单元，并确定是否重新排序 行内的单元允许相邻行的进一步压缩。 该方法还包括重新排序行内的单元，以允许相邻行的进一步压缩。 该方法还包括垂直分割行以最小化分割行之间的距离的步骤。

公开(公告)号：US06550046B1

公开(公告)日：2003-04-15

申请号：US09411417

申请日：1999-10-01

申请人： Florin Balasa ,  Koen Lampaert

发明人： Florin Balasa ,  Koen Lampaert

IPC分类号： G06F1750

CPC分类号： G06F17/5072

摘要： An automated method for packing cells in the generation of an integrated circuit design layout that is especially useful for circuits having symmetry constraints, which is the case for most analog circuits, uses sequence pair encoding and simulated annealing. From the set of all cells needed to implement the circuit, subsets of the cells are defined that must exhibit symmetry. Symmetry constraints are defined for each subset and the cells are encoded as ordered sequence-pairs. To reduce the solution space, the initial sequence pair encoding is required to be symmetry-feasible and the annealer subspace is limited to symmetry-feasible sequence-pairs.

摘要翻译： 在生成集成电路设计布局中的单元的自动化方法，其对于具有对称约束的电路特别有用，对于大多数模拟电路而言，使用序列对编码和模拟退火。 从实现电路所需的所有单元的集合中，定义必须具有对称性的单元的子集。 为每个子集定义对称约束，并将单元格作为有序序列对编码。 为了减少解空间，初始序列对编码需要对称可行，退火子空间被限制为对称可行的序列对。

公开(公告)号：US06588002B1

公开(公告)日：2003-07-01

申请号：US09941883

申请日：2001-08-28

申请人： Koen Lampaert ,  Andy Brotman ,  Paolo Miliozzi ,  Paramjit Singh ,  Mishel Matloubian ,  Bijan Bhattacharyya ,  Francis M Rotella ,  Rajesh Divecha

发明人： Koen Lampaert ,  Andy Brotman ,  Paolo Miliozzi ,  Paramjit Singh ,  Mishel Matloubian ,  Bijan Bhattacharyya ,  Francis M Rotella ,  Rajesh Divecha

IPC分类号： G06F1750

CPC分类号： G06F17/5068 ,  G06F17/5063

摘要： In one embodiment, a number of parameter values for an inductor, such as a spiral inductor, are received. Examples of the parameter values are Number of Turns, Spacing, Width, Xsize, and Ysize parameter values. From the received parameter values, a number of parasitic values for a subcircuit model of the inductor are determined. For example, parasitic resistor values and parasitic capacitor values of the inductor are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the circuit comprising the inductor. An inductor layout is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the circuit comprising the inductor. As such, the parasitic values of the inductor have already been taken into account in the initial circuit simulation and, there is no need to extract the internal parasitics of the inductor for further circuit simulations.

摘要翻译： 在一个实施例中，接收诸如螺旋电感器的电感器的多个参数值。 参数值的示例是Turns，Spacing，Width，Xsize和Ysize参数值。 从接收到的参数值中，确定电感器的子电路模型的寄生值的数量。 例如，确定电感器的寄生电阻值和寄生电容值。 寄生电阻值和寄生电容值用于模拟包括电感的电路。 然后产生电感器布局，其产生与在模拟包括电感器的电路中已经使用的寄生值相同的寄生值。 因此，在初始电路仿真中已经考虑了电感器的寄生值，并且不需要提取电感器的内部寄生效应用于进一步的电路仿真。

公开(公告)号：US06728942B2

公开(公告)日：2004-04-27

申请号：US09879142

申请日：2001-06-12

申请人： Koen Lampaert ,  Andy Brotman ,  Paolo Miliozzi ,  Paramjit Singh ,  Mishel Matloubian ,  Bijan Bhattacharyya

发明人： Koen Lampaert ,  Andy Brotman ,  Paolo Miliozzi ,  Paramjit Singh ,  Mishel Matloubian ,  Bijan Bhattacharyya

IPC分类号： G06F1750

CPC分类号： G06F17/5068

摘要： In one disclosed embodiment, a number of parameter values for an RF MOSFET are received. Examples of parameter values are style, bulk contact, finger width, finger length, number of fingers, current, and slice parameter values. From the received parameter values, a number of parasitic values for a subcircuit model of the RF MOSFET are determined. For example, parasitic resistor values and parasitic capacitor values of the RF MOSFET are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the circuit comprising the RF MOSFET. An RF MOSFET layout is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the circuit comprising the RF MOSFET. As such, the parasitic values of the RF MOSFET have already been taken into account in the initial circuit simulation.

摘要翻译： 在一个公开的实施例中，接收RF MOSFET的多个参数值。 参数值的示例是样式，批量接触，手指宽度，手指长度，手指数，当前和切片参数值。 根据接收的参数值，确定RF MOSFET的子电路模型的寄生数值。 例如，确定RF MOSFET的寄生电阻值和寄生电容值。 寄生电阻值和寄生电容值用于模拟包括RF MOSFET的电路。 然后产生RF MOSFET布局，其导致寄生值与在模拟包括RF MOSFET的电路中已经使用的寄生值相同。 因此，在初始电路仿真中已经考虑了RF MOSFET的寄生值。