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公开(公告)号：US6081883A
公开(公告)日：2000-06-27
申请号：US985996
申请日：1997-12-05
申请人： Paul Popelka , Tarun Kumar Tripathy , Richard Allen Walter , Paul Brian Del Fante , Murali Sundaramoorthy Repakula , Lakshman Narayanaswamy , Donald Wayne Sterk , Amod Prabhakar Bodas , Leslie Thomas McCutcheon , Daniel Murray Jones , Peter Kingsley Craft , Clive Mathew Philbrick , David Allan Higgen , Edward John Row
发明人： Paul Popelka , Tarun Kumar Tripathy , Richard Allen Walter , Paul Brian Del Fante , Murali Sundaramoorthy Repakula , Lakshman Narayanaswamy , Donald Wayne Sterk , Amod Prabhakar Bodas , Leslie Thomas McCutcheon , Daniel Murray Jones , Peter Kingsley Craft , Clive Mathew Philbrick , David Allan Higgen , Edward John Row
CPC分类号： G06F12/0813 , G06F17/30067
摘要： A scalable computer system has an interconnect bus providing communication links among a host processor and one or more function-specific processors, including a network processor (NP) and a file storage processor (FSP). The host processor provides a single interface to network administrators for maintaining the system. A bi-endian conversion system is provided to minimize a need for translating between big and little endian data types generated by diverse processors. The NP shares a single memory image with other processors and has a buffer memory for buffering requests from the network interfaces. The buffer memory has one or more segments which are dynamically allocatable to different processors. The FSP has a metadata cache for maintaining information on data being cached in the NP buffer memory. The FSP also has a write cache for buffering file write operations directed at disks. Upon receiving requests for data from the NP, the FSP checks the metadata cache to see if a copy of the requested data has been cached in the NP buffer and, if the copy exists in the NP buffer, causing the NP with the data to respond to the request. The resulting scalable computer provides higher data availability, faster access to shared data, and reduced administrative costs via data consolidation.
摘要翻译： 可扩展计算机系统具有互连总线，其提供主机处理器和一个或多个功能特定处理器（包括网络处理器（NP））和文件存储处理器（FSP）之间的通信链路。 主机处理器为网络管理员提供单一接口，用于维护系统。 提供双端转换系统以最小化对由不同处理器生成的大端和小端数据类型之间的转换的需要。 NP与其他处理器共享单个存储器映像，并具有用于缓冲来自网络接口的请求的缓冲存储器。 缓冲存储器具有一个或多个可动态分配给不同处理器的段。 FSP具有元数据缓存，用于维护关于缓冲在NP缓冲存储器中的数据的信息。 FSP还具有缓存用于缓冲针对磁盘的文件写入操作的写缓存。 在接收到来自NP的数据的请求时，FSP检查元数据缓存以查看所请求的数据的副本是否已被缓存在NP缓冲器中，并且如果副本存在于NP缓冲器中，则导致NP数据响应 要求。 所产生的可扩展计算机提供更高的数据可用性，更快地访问共享数据，并通过数据合并降低管理成本。
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公开(公告)号：US5931918A
公开(公告)日：1999-08-03
申请号：US902790
申请日：1997-07-30
CPC分类号： G06F17/30224 , H04L29/06 , H04L67/40 , H04L67/42 , H04L69/329
摘要： A file server architecture is disclosed, comprising as separate processors, a network controller unit, a file controller unit and a storage processor unit. These units incorporate their own processors, and operate in parallel with a local Unix host processor. All networks are connected to the network controller unit, which performs all protocol processing up through the NFS layer. The virtual file system is implemented in the file control unit, and the storage processor provides high-speed multiplexed access to an array of mass storage devices. The file controller unit control file information caching through its own local cache buffer, and controls disk data caching through a large system memory which is accessible on a bus by any of the processors.
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公开(公告)号：US5802366A
公开(公告)日：1998-09-01
申请号：US320451
申请日：1994-10-11
CPC分类号： G06F17/30224 , H04L29/06 , H04L67/40 , H04L67/42 , H04L69/329
摘要： A file server architecture is disclosed, comprising as separate processors, a network controller unit, a file controller unit and a storage processor unit. These units incorporate their own processors, and operate in parallel with a local Unix host processor. All networks are connected to the network controller unit, which performs all protocol processing up through the NFS layer. The virtual file system is implemented in the file control unit, and the storage processor provides high-speed multiplexed access to an array of mass storage devices. The file controller unit control file information caching through its own local cache buffer, and controls disk data caching through a large system memory which is accessible on a bus by any of the processors.
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