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1.发明授权Method of generating data for estimating resource requirements for a circuit design 有权生成用于估计电路设计的资源需求的数据的方法公开(公告)号：US09117046B1
公开(公告)日：2015-08-25
申请号：US12041167
申请日：2008-03-03
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054 , G06F2217/72
摘要： A method of generating data for estimating resource requirements for a circuit design is disclosed. The method comprises identifying a plurality of intermediate circuit modules of netlists for circuit designs; elaborating each intermediate circuit module of the plurality of intermediate circuit modules according to an associated plurality of parameter sets; generating an estimate of resources for each intermediate circuit module and parameter set of the associated plurality of parameter sets; and storing the estimates of resources for the intermediate circuit modules.
摘要翻译： 公开了一种生成用于估计电路设计的资源需求的数据的方法。 该方法包括识别用于电路设计的网表的多个中间电路模块; 根据相关联的多个参数集详细描述多个中间电路模块的每个中间电路模块; 生成每个中间电路模块的资源估计和相关联的多个参数集的参数集合; 并存储用于中间电路模块的资源估计。
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公开(公告)号：US07979835B1
公开(公告)日：2011-07-12
申请号：US12041182
申请日：2008-03-03
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method of estimating resource requirements for a circuit design is disclosed. The method comprises identifying intermediate circuit modules of a netlist associated with the circuit design; accessing a library of resource requirements for intermediate circuit modules of netlists for circuit designs; selecting intermediate circuit modules of the library according to predetermined parameters for the circuit design; and generating an estimate of resource requirements for the circuit design based upon resource requirements of the selected intermediate circuit modules.
摘要翻译： 公开了一种估计电路设计的资源需求的方法。 该方法包括识别与电路设计相关联的网表的中间电路模块; 访问电路设计网表的中间电路模块的资源需求库; 根据电路设计的预定参数选择库的中间电路模块; 以及基于所选择的中间电路模块的资源需求生成对电路设计的资源需求的估计。
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公开(公告)号：US07886256B1
公开(公告)日：2011-02-08
申请号：US12146507
申请日：2008-06-26
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Approaches for determining a static timing analysis of a logic design are disclosed. Physical delay arcs of a plurality of physical elements of an integrated circuit specify respective propagation delays from inputs of the physical elements to outputs of the physical elements. Logic components of the logic design are mapped to selected ones of the physical components of the physical elements. For each of the logic components, the logic delay arcs are determined from the physical delay arcs. Each logic delay arc for each logic component specifies a propagation delay from an input of the logic component to an output of the logic component. A static timing analysis of the logic components is performed using the logic delay arc, and data from the timing analysis is output.
摘要翻译： 公开了用于确定逻辑设计的静态时序分析的方法。 集成电路的多个物理元件的物理延迟弧指定从物理元件的输入到物理元件的输出的相应传播延迟。 逻辑设计的逻辑组件被映射到物理元件的物理组件中的选定的一部分。 对于每个逻辑组件，逻辑延迟弧由物理延迟弧确定。 每个逻辑组件的每个逻辑延迟弧指定从逻辑组件的输入到逻辑组件的输出的传播延迟。 使用逻辑延迟弧执行逻辑组件的静态时序分析，并输出来自定时分析的数据。
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