公开(公告)号：US4979100A

公开(公告)日：1990-12-18

申请号：US176654

申请日：1988-04-01

申请人： Perry Makris ,  Frederick Choi ,  Mark Klimek ,  James Mapp ,  Koji Munemoto ,  Jeff Nicoll ,  Mark Soderberg ,  James A. Moore

发明人： Perry Makris ,  Frederick Choi ,  Mark Klimek ,  James Mapp ,  Koji Munemoto ,  Jeff Nicoll ,  Mark Soderberg ,  James A. Moore

IPC分类号： G06F13/36 ,  G06F13/362 ,  H04J3/02 ,  H04L12/56

CPC分类号： G06F13/362 ,  H04L12/56

摘要： A packet switch receives data and processes it for assembly into packages. A bus allows communication between each of the data processing units of the switch and one or more storage units for storing the data packets. Arbitration for deciding which of the processing units will be granted access to the bus is performed by a system which selectively and alterably designates any of at least two different levels of priority of access to the bus for each of the processing units, and the relative percentages of time of access for the different priorty levels. The system assures greater access to the bus by those of the processing units having the higher level of priority. If communication is provided by two buses, the requests for access are alternated between them. The arbitration system provides selective access to the bus in any of a plurality of bus cycles including a read cycle, a write cycle and a read/modify/write cycle, and grants a request for access from a higher priority processing unit within one bus cycle.

摘要翻译： 分组交换机接收数据并处理它以便组装成包。 总线允许交换机的每个数据处理单元与用于存储数据分组的一个或多个存储单元之间的通信。 用于决定哪个处理单元将被授权访问总线的仲裁由系统执行，该系统选择性地和可变地指定对于每个处理单元访问总线的至少两个不同级别的优先级，并且相对百分比 的不同优先级别的访问时间。 该系统通过具有较高优先级的处理单元的那些来确保对总线的更大的访问。 如果通过两条总线提供通信，则访问请求在它们之间交替。 仲裁系统以包括读周期，写周期和读/修/写周期在内的多个总线周期中的任一个提供对总线的选择性访问，并且在一个总线周期内授予来自较高优先级处理单元的访问请求 。