公开(公告)号：US07584449B2

公开(公告)日：2009-09-01

申请号：US11271323

申请日：2005-11-10

申请人： Peter Beerel ,  Andrew Lines ,  Michael Davies

发明人： Peter Beerel ,  Andrew Lines ,  Michael Davies

IPC分类号： G06F17/50

CPC分类号： G06F17/5059

摘要： Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.

摘要翻译： 描述了用于优化电路设计的方法和装置。 产生对应于电路设计的门级电路描述。 门级电路描述包括跨越多个级别的多条管道。 使用线性编程技术，将最少数量的缓冲区添加到选定的管道中，使得满足性能约束。

公开(公告)号：US08051396B2

公开(公告)日：2011-11-01

申请号：US12435270

申请日：2009-05-04

申请人： Peter Beerel ,  Andrew Lines ,  Michael Davies

发明人： Peter Beerel ,  Andrew Lines ,  Michael Davies

IPC分类号： G06F17/50

CPC分类号： G06F17/5059

摘要： Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.

摘要翻译： 描述了用于优化电路设计的方法和装置。 产生对应于电路设计的门级电路描述。 门级电路描述包括跨越多个级别的多条管道。 使用线性编程技术，将最少数量的缓冲区添加到选定的管道中，使得满足性能约束。

公开(公告)号：US20090217232A1

公开(公告)日：2009-08-27

申请号：US12435270

申请日：2009-05-04

申请人： Peter Beerel ,  Andrew Lines ,  Michael Davies

发明人： Peter Beerel ,  Andrew Lines ,  Michael Davies

IPC分类号： G06F17/50

CPC分类号： G06F17/5059

摘要： Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.

摘要翻译： 描述了用于优化电路设计的方法和装置。 产生对应于电路设计的门级电路描述。 门级电路描述包括跨越多个级别的多条管道。 使用线性编程技术，将最少数量的缓冲区添加到选定的管道中，使得满足性能约束。

公开(公告)号：US20060120189A1

公开(公告)日：2006-06-08

申请号：US11271323

申请日：2005-11-10

申请人： Peter Beerel ,  Andrew Lines ,  Michael Davies

发明人： Peter Beerel ,  Andrew Lines ,  Michael Davies

IPC分类号： G11C7/00

CPC分类号： G06F17/5059

摘要： Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.

公开(公告)号：US06785875B2

公开(公告)日：2004-08-31

申请号：US10354272

申请日：2003-01-28

申请人： Peter Beerel ,  Andrew Lines ,  Qing Wu

发明人： Peter Beerel ,  Andrew Lines ,  Qing Wu

IPC分类号： G06F945

CPC分类号： G06F17/5059 ,  G06F17/505 ,  G06F17/5068

摘要： Methods and apparatus are described for facilitating physical synthesis of an integrated circuit design. A set of paths between observable nodes in a netlist representing the circuit design is generated. Each path corresponds to a sequence of signal transitions. Transistors represented in the netlist are sized to attempt to meet a delay constraint for each path. The delay constraint corresponds to a unit delay times the number of signal transitions in the corresponding path. A plurality of individual delays of different durations are allocated among the transitions for at least one of the paths to meet the delay constraint. At least one of the individual delays exceeds the unit delay.

公开(公告)号：US06854096B2

公开(公告)日：2005-02-08

申请号：US10620330

申请日：2003-07-14

申请人： Frederik Eaton ,  Peter Beerel

发明人： Frederik Eaton ,  Peter Beerel

IPC分类号： G06F17/50

CPC分类号： G06F17/5059 ,  G06F17/505 ,  G06F17/5068

摘要： Methods and apparatus are described for facilitating physical synthesis of a circuit design. The circuit design includes a plurality cell instances organized hierarchically. Each cell instance corresponds schematically to one of a plurality of cell types. Transistors in each of the cell instances is sized with reference to an objective function thereby resulting in a first plurality of cell subtypes for each cell type. Each cell subtype corresponding to a particular cell type differs from all other cell subtypes corresponding to the particular cell type by at least one transistor dimension. Selected ones of the subtypes for at least one of the cell types are merged thereby resulting in a second plurality of subtypes for the at least one of the cell types. The second plurality of subtypes being fewer than the first plurality of subtypes. The merging of the selected subtypes achieves a balance between the objective function and a cost associated with maintaining the selected subtypes distinct.

摘要翻译： 描述了用于促进电路设计的物理合成的方法和装置。 电路设计包括分层组织的多个小区实例。 每个单元实例示意性地对应于多个单元类型之一。 每个细胞实例中的晶体管参考目标函数来定尺寸，从而导致每个细胞类型的第一多个细胞亚型。 对应于特定细胞类型的每个细胞亚型与通过至少一个晶体管尺寸对应于特定细胞类型的所有其它细胞亚型不同。 合并至少一种细胞类型的选择的子类型，从而导致用于至少一种细胞类型的第二多个亚型。 所述第二多个亚型比所述第一多个亚型少。 所选子类型的合并实现了目标函数与维持选定子类型不同的成本之间的平衡。