公开(公告)号：US20210352231A1

公开(公告)日：2021-11-11

申请号：US16867539

申请日：2020-05-05

Applicant: PixArt Imaging Incorporation

Inventor： Ren-Chieh Liu ,  Wen-Cheng Yen ,  Hsin-Hung Shen

IPC: H04N5/355

Abstract: A method of operating an HDR pixel circuit includes: establishing a calibration full-well capacity of a photodiode according to a first predetermined voltage level; over-charging both the photodiode and a floating diffusion node; dissipating the charges of the floating diffusion node and the charges on the photodiode so that the charges on the photodiode are substantially equal to the calibration full-well capacity; transferring the charges on the photodiode to the floating diffusion node; and sensing a voltage on the floating diffusion node to generate a calibration signal related to the calibration full-well capacity.

公开(公告)号：US11343448B2

公开(公告)日：2022-05-24

申请号：US16867539

申请日：2020-05-05

Applicant: PixArt Imaging Incorporation

Inventor： Ren-Chieh Liu ,  Wen-Cheng Yen ,  Hsin-Hung Shen

IPC: H04N5/355

Abstract: A method of operating an HDR pixel circuit includes: establishing a calibration full-well capacity of a photodiode according to a first predetermined voltage level; over-charging both the photodiode and a floating diffusion node; dissipating the charges of the floating diffusion node and the charges on the photodiode so that the charges on the photodiode are substantially equal to the calibration full-well capacity; transferring the charges on the photodiode to the floating diffusion node; and sensing a voltage on the floating diffusion node to generate a calibration signal related to the calibration full-well capacity.

公开(公告)号：US11153524B1

公开(公告)日：2021-10-19

申请号：US17028945

申请日：2020-09-22

Applicant: PixArt Imaging Incorporation

Inventor： Wen-Cheng Yen ,  Ren-Chieh Liu

IPC: H04N5/378 ,  H04N5/363 ,  H04N5/355

Abstract: The present invention provides a pixel circuit. A first S/H stage and the second S/H stage are connected in cascade between a buffer amplifier and an amplifier circuit. During a first and a second time period, a buffered output signal having a first voltage and a second voltage generated by the buffer amplifier are stored serially to the first S/H stage and the second S/H stage. The amplifier circuit senses the first voltage and the second voltage stored in the first S/H stage and the second S/H stage independently for generating a first output signal and a second output signal correspondingly. A calibrated signal is generated according to the first output signal and the second output signal.