公开(公告)号：US20250093931A1

公开(公告)日：2025-03-20

申请号：US18468242

申请日：2023-09-15

Applicant: QUALCOMM Incorporated

Inventor： Mahadevamurty Nemani ,  Anubhav Mishra ,  Arun Sukheja ,  Nitin Makhija ,  Adarsh Baraka Ravi

IPC: G06F1/28 ,  G06F9/445

Abstract: Autonomously managing core cluster frequencies using performance statistics in processor devices is disclosed herein. In some aspects, a cluster power management circuit of a processor device collects Activity Management Unit (AMU) statistics for multiple processor cores for each of one or more frequency operating points over a time interval. Based on the AMU statistics, the cluster power management circuit generates a performance model representing processor performance as a function of frequency, and uses the performance model and a power consumption measurement to generate an energy-per-instruction (EI) model representing energy per instruction as a function of frequency. The cluster power management circuit then generates an advantage model based on a first rate of change of the performance model as a function of frequency and a second rate of change of the EI model as a function of frequency, and identifies a target frequency operating point based on the advantage model.

公开(公告)号：US20250093942A1

公开(公告)日：2025-03-20

申请号：US18469890

申请日：2023-09-19

Applicant: QUALCOMM Incorporated

Inventor： Mahadevamurty Nemani ,  Adarsh Baraka Ravi ,  Nitin Makhija ,  Pradeep Kanapathipillai

IPC: G06F1/3296 ,  G06F1/3206

Abstract: Power sources provide power in a range with a maximum supply voltage provided under zero-load current conditions. Power circuits in an IC receive and aggregate indications of load current from processor circuits in processor circuit clusters and, reduce power consumption in the IC during zero or low load current conditions by generating a voltage control signal to reduce the supply voltage. Reducing the no-load voltage also reduces stress on gate oxides of transistors in the IC to increase oxide longevity. Based on the aggregated load current indications, which is periodically updated, the no-load supply voltage may be incrementally reduced down to a voltage threshold over the course of multiple periods. In some examples, the power circuits receive throttle signals when the processor circuits are throttled due to a voltage droop, and such signals may cause the power circuits to generate a control signal to increase the no-load voltage.