MIXED-WIDTH SIMD OPERATIONS USING EVEN/ODD REGISTER PAIRS FOR WIDE DATA ELEMENTS
    1.
    发明申请
    MIXED-WIDTH SIMD OPERATIONS USING EVEN/ODD REGISTER PAIRS FOR WIDE DATA ELEMENTS 审中-公开
    使用偶数/ ODD寄存器对进行宽数据元素的混合宽度SIMD操作

    公开(公告)号:US20170024209A1

    公开(公告)日:2017-01-26

    申请号:US14805456

    申请日:2015-07-21

    Abstract: Systems and methods relate to a mixed-width single instruction multiple data (SIMD) instruction which has at least a source vector operand comprising data elements of a first bit-width and a destination vector operand comprising data elements of a second bit-width, wherein the second bit-width is either half of or twice the first bit-width. Correspondingly, one of the source or destination vector operands is expressed as a pair of registers, a first register and a second register. The other vector operand is expressed as a single register. Data elements of the first register correspond to even-numbered data elements of the other vector operand expressed as a single register, and data elements of the second register correspond to data elements of the other vector operand expressed as a single register.

    Abstract translation: 系统和方法涉及混合宽度单指令多数据(SIMD)指令,其具有至少包括第一位宽的数据元素和包含第二位宽的数据元素的目的地向量操作数的源向量操作数,其中 第二个位宽是第一个位宽的一半或两倍。 相应地,源或目标向量操作数之一被表示为一对寄存器,第一寄存器和第二寄存器。 另一个向量操作数表示为单个寄存器。 第一寄存器的数据元素对应于表示为单个寄存器的另一向量操作数的偶数数据元,第二寄存器的数据元对应于表示为单个寄存器的另一向量操作数的数据元。

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